公开(公告)号：US20230197522A1

公开(公告)日：2023-06-22

申请号：US18065130

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack. The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

公开(公告)号：US20190273115A1

公开(公告)日：2019-09-05

申请号：US16419576

申请日：2019-05-22

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L27/06 ,  H01L21/768 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/822

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US20230197830A1

公开(公告)日：2023-06-22

申请号：US18065353

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/40 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/3213 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/401 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/42392

Abstract: A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.

公开(公告)号：US20230197726A1

公开(公告)日：2023-06-22

申请号：US18064508

申请日：2022-12-12

Applicant: IMEC VZW

Inventor： Book Teik Chan ,  Dunja Radisic ,  Anne Vandooren ,  Juergen Boemmels

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  H01L21/823828 ,  H01L29/0673

Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.

公开(公告)号：US10367031B2

公开(公告)日：2019-07-30

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L23/40 ,  H01L27/148 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/8258 ,  B28D1/00 ,  H01L21/304 ,  H01L31/0224

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US20180076260A1

公开(公告)日：2018-03-15

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L31/0216 ,  H01L29/417

CPC classification number: H01L27/14875 ,  B28D1/005 ,  H01L21/304 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/0694 ,  H01L29/41708 ,  H01L31/02164 ,  H01L31/022408

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.