公开(公告)号：US09716480B2

公开(公告)日：2017-07-25

申请号：US15269588

申请日：2016-09-19

Applicant: INPHI CORPORATION

Inventor： James Lawrence Gorecki ,  Irene Quek

IPC: H03F3/08 ,  H03G3/30 ,  H03F3/45 ,  H03G1/00 ,  H03F1/08 ,  H03F3/30 ,  H04B10/2507 ,  H04B10/69

CPC classification number: H03G3/3084 ,  H03F1/086 ,  H03F3/082 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45224 ,  H03F2203/45288 ,  H03G1/0035 ,  H04B10/2507 ,  H04B10/6911

Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

公开(公告)号：US09866231B2

公开(公告)日：2018-01-09

申请号：US15426506

申请日：2017-02-07

Applicant: INPHI CORPORATION

Inventor： Michael Le ,  James Gorecki ,  Jamal Riani ,  Jorge Pernillo ,  Amber Tan ,  Karthik Gopalakrishnan ,  Belal Helal ,  Chang-Feng Loi ,  Irene Quek ,  Guojun Ren

IPC: H04L25/03 ,  H03M1/38 ,  H03M1/12 ,  H03L7/10

CPC classification number: H03M1/38 ,  H03M1/0604 ,  H03M1/1038 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/468 ,  H04L25/03012 ,  H04L25/03019 ,  H04L25/03878

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

公开(公告)号：US09602116B1

公开(公告)日：2017-03-21

申请号：US14990309

申请日：2016-01-07

Applicant: INPHI CORPORATION

Inventor： Michael Le ,  James Gorecki ,  Jamal Riani ,  Jorge Pernillo ,  Amber Tan ,  Karthik Gopalakrishnan ,  Belal Helal ,  Chang-Feng Loi ,  Irene Quek ,  Guojun Ren

IPC: H03M1/06 ,  H03L7/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/46 ,  H04L25/03

CPC classification number: H03M1/38 ,  H03M1/0604 ,  H03M1/1038 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/468 ,  H04L25/03012 ,  H04L25/03019 ,  H04L25/03878

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

公开(公告)号：US10411684B2

公开(公告)日：2019-09-10

申请号：US16153248

申请日：2018-10-05

Applicant: INPHI CORPORATION

Inventor： Irene Quek

IPC: H03K5/13 ,  H03K5/135 ,  H03M1/86 ,  H03K5/00 ,  H04L27/38

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.

公开(公告)号：US10128827B1

公开(公告)日：2018-11-13

申请号：US15343608

申请日：2016-11-04

Applicant: INPHI CORPORATION

Inventor： Irene Quek

IPC: H03K5/135 ,  H03M1/86 ,  H03K5/00 ,  H04L27/38

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.

公开(公告)号：US09473090B2

公开(公告)日：2016-10-18

申请号：US14550842

申请日：2014-11-21

Applicant: INPHI CORPORATION

Inventor： James Lawrence Gorecki ,  Irene Quek

IPC: H03F3/08 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00 ,  H03F1/08 ,  H03F3/30

CPC classification number: H03G3/3084 ,  H03F1/086 ,  H03F3/082 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45224 ,  H03F2203/45288 ,  H03G1/0035 ,  H04B10/2507 ,  H04B10/6911

Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

Abstract translation: 本公开涉及用于多级光通信的放大器领域，更具体地涉及具有增益控制的跨阻抗放大器（TIA）的技术。 所要求保护的实施例解决了实现具有高线性度，低噪声，低功率和宽带宽的低成本TIA的问题。 更具体地，一些权利要求涉及用于使用由反馈环路控制的多个基于逆变器的复制增益控制单元来提供TIA增益控制的方法，以管理进入放大输出级的电流，从而管理TIA输出电压。