公开(公告)号：US20230420456A1

公开(公告)日：2023-12-28

申请号：US17850782

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Imola ZIGONEANU ,  Gilbert DEWEY ,  Anant H. JAHAGIRDAR ,  Harold W. KENNEL ,  Pratik PATEL ,  Anand S. MURTHY ,  Chi-Hing CHOI ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/161 ,  H01L29/167

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.

公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC: H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20220310600A1

公开(公告)日：2022-09-29

申请号：US17842450

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Harold W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L21/8258 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20220165737A1

公开(公告)日：2022-05-26

申请号：US17667498

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Van H. LE ,  Gilbert DEWEY ,  Abhishek A. SHARMA

IPC: H01L27/108

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

公开(公告)号：US20210407902A1

公开(公告)日：2021-12-30

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Mengcheng LU ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Eric Charles MATTSON

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US20210296180A1

公开(公告)日：2021-09-23

申请号：US17336565

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Willy RACHMADY ,  Anand S. MURTHY ,  Chandra S. MOHAPATRA ,  Tahir GHANI ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L21/8234 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

公开(公告)号：US20200312841A1

公开(公告)日：2020-10-01

申请号：US16367175

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Caleb BARRETT ,  Jay P. GUPTA ,  Nishant GUPTA ,  Kaiwen HSU ,  Byungki JUNG ,  Aravind S. KILLAMPALLI ,  Justin RAILSBACK ,  Supanee SUKRITTANON ,  Prashant WADHWA

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

公开(公告)号：US20200287036A1

公开(公告)日：2020-09-10

申请号：US16645758

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/205 ,  H01L29/15 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20200066843A1

公开(公告)日：2020-02-27

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Cheng-Ying HUANG ,  Harold W. KENNEL ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.