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    Subtractive Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects
    1.
    发明申请
    Subtractive Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects 审中-公开
    用于后端（BEOL）互连的减法自对准通孔和插头图案

    公开(公告)号：US20160197011A1

    公开(公告)日：2016-07-07

    申请号：US14912036

    申请日：2013-09-27

    Applicant: INTEL CORPORATION

    Inventor： ROBERT L. BRISTOL ,  FLORIAN GSTREIN ,  RICHARD E. SCHENKER ,  PAUL A. NYHUS ,  CHARLES H. WALLACE ,  HUI JAE YOO

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

    Abstract translation: 描述了用于后端（BEOL）互连的消减自对准通孔和插塞图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 互连结构还包括设置在互连结构的第一层上方的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有低于金属线的最下表面的最下表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一光栅的金属线与第二光栅的金属线间隔开。

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    4.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200294998A1

    公开(公告)日：2020-09-17

    申请号：US16355195

    申请日：2019-03-15

    Applicant: INTEL CORPORATION

    Inventor： AARON D. LILAK ,  EHREN MANNEBACH ,  ANH PHAN ,  RICHARD E. SCHENKER ,  STEPHANIE A. BOJARSKI ,  WILLY RACHMADY ,  PATRICK R. MORROW ,  JEFFERY D. BIELEFELD ,  GILBERT DEWEY ,  HUI JAE YOO

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/532

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

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