公开(公告)号：US20190206942A1

公开(公告)日：2019-07-04

申请号：US16192220

申请日：2018-11-15

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/105 ,  H01L21/311

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20190044061A1

公开(公告)日：2019-02-07

申请号：US16147159

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Pavan Kumar Reddy Aella ,  Kolya Yastrebenetsky ,  Masuji Honjo

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of thePCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.

公开(公告)号：US11647638B2

公开(公告)日：2023-05-09

申请号：US16295687

申请日：2019-03-07

Applicant: INTEL CORPORATION

Inventor： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

IPC: H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

公开(公告)号：US11367833B2

公开(公告)日：2022-06-21

申请号：US16147159

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Pavan Kumar Reddy Aella ,  Kolya Yastrebenetsky ,  Masuji Honjo

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.

公开(公告)号：US12239032B2

公开(公告)日：2025-02-25

申请号：US17733723

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Pavan Kumar Reddy Aella ,  Kolya Yastrebenetsky ,  Masuji Honjo

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/10 ,  H10N70/00

Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.

公开(公告)号：US20170271412A1

公开(公告)日：2017-09-21

申请号：US15612245

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L23/00 ,  H01L21/311 ,  H01L23/522 ,  H01L27/105 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20170186815A1

公开(公告)日：2017-06-29

申请号：US14998194

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L27/105 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US10134809B2

公开(公告)日：2018-11-20

申请号：US15612245

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L27/105 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20220263019A1

公开(公告)日：2022-08-18

申请号：US17733723

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Pavan Kumar Reddy Aella ,  Kolya Yastrebenetsky ,  Masuji Honjo

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.

公开(公告)号：US09704923B1

公开(公告)日：2017-07-11

申请号：US14998194

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522 ,  H01L27/105

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.