公开(公告)号：US20170098709A1

公开(公告)日：2017-04-06

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： NEVILLE L. DIAS ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  ROMAN W. OLAC-VAW ,  HSU-YU CHANG ,  TING CHANG ,  RAHUL RAMASWAMY ,  PEI-CHI LIU

IPC: H01L29/78 ,  H01L29/10 ,  H03D7/14 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

Abstract: An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.

公开(公告)号：US20200043914A1

公开(公告)日：2020-02-06

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  RAHUL RAMASWAMY ,  NIDHI NIDHI ,  CHEN-GUAN LEE

IPC: H01L27/06 ,  H01L27/088 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：US20170103923A1

公开(公告)日：2017-04-13

申请号：US15127839

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： NIDHI NIDHI ,  CHIA-HONG JAN ,  ROMAN W. OLAC-VAW ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  WALID M. HAFEZ ,  RAHUL RAMASWAMY

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.