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    Fused adjacent memory stores
    2.
    发明授权
    Fused adjacent memory stores 有权

    公开(公告)号：US10216516B2

    公开(公告)日：2019-02-26

    申请号：US15281957

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

    IPC: G06F9/312 ,  G06F9/34 ,  G06F3/00 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

    Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

    INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS
    4.
    发明申请
    INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS 审中-公开
    指令和逻辑的调度说明

    公开(公告)号：US20160274944A1

    公开(公告)日：2016-09-22

    申请号：US15056782

    申请日：2016-02-29

    Applicant: Intel Corporation

    Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

    IPC: G06F9/50

    CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

    Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

    Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的电路，以及基于确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的电路，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。

    APPARATUSES AND METHODS TO ASSIGN A LOGICAL THREAD TO A PHYSICAL THREAD
    7.
    发明申请
    APPARATUSES AND METHODS TO ASSIGN A LOGICAL THREAD TO A PHYSICAL THREAD 审中-公开
    将逻辑螺纹分配到物理螺纹的装置和方法

    公开(公告)号：US20160266905A1

    公开(公告)日：2016-09-15

    申请号：US14644130

    申请日：2015-03-10

    Applicant: Intel Corporation

    Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Rainer Theuer ,  Gregor Stellpflug ,  Tyler N. Sondag

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3851 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/4552 ,  G06F9/5027 ,  G06F2209/5018

    Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.

    Abstract translation: 将逻辑线程分配给物理线程的方法和装置。 在一个实施例中，一种装置包括数据存储装置，其存储当由硬件处理器执行时使得硬件处理器执行以下操作的代码：将指令转换为转换的指令，为翻译的指令分配逻辑线程， 线程图提示翻译指令; 以及硬件调度器，用于分配硬件处理器的物理线程以基于线程图提示来执行逻辑线程。

    Handling of binary translated self modifying code and cross modifying code
    8.
    发明授权
    Handling of binary translated self modifying code and cross modifying code 有权
    处理二进制翻译自修改代码和交叉修改代码

    公开(公告)号：US09116729B2

    公开(公告)日：2015-08-25

    申请号：US13997694

    申请日：2012-12-27

    Applicant: Intel Corporation

    Inventor： Nirajan L. Cooray ,  David Keppel ,  Naveen Kumar ,  Ori Lempel ,  Michael Neilly ,  Naveen Neelakantam ,  H. Peter Anvin ,  Sebastian Winkel

    IPC: G06F9/455 ,  G06F12/10

    CPC classification number: G06F9/45525

    Abstract: A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

    Abstract translation: 处理器包括处理器核，用于执行从存储在存储器的第一页中的第一指令转换的第一翻译指令。 处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。 在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。 其他实施例被描述为所要求保护的。

    Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
    9.
    发明授权
    Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment 有权
    从部分仿真环境中的源代码指令集架构（ISA）代码转换为翻译代码

    公开(公告)号：US08762127B2

    公开(公告)日：2014-06-24

    申请号：US13785561

    申请日：2013-03-05

    Applicant: Intel Corporation

    Inventor： Sebastian Winkel ,  Koichi Yamada ,  Suresh Srinivas ,  James E. Smith

    IPC: G06F9/445 ,  G06F9/30 ,  G06F12/08

    CPC classification number: G06F9/3017 ,  G06F9/455 ,  G06F12/0873 ,  G06F12/0875

    Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器可以在多种模式下操作，包括直接执行模式和仿真执行模式。 更具体地，处理器可以在部分仿真模型中操作，其中以直接执行模式直接处理源指令集架构（ISA）指令，并且在仿真执行模式中处理由仿真引擎生成的转换代码。 实施例还可以使用可以存储在处理器的一个或多个存储器和系统中的其他地方的信息来提供模式之间的有效转换。 描述和要求保护其他实施例。

    Instruction and logic for predication and implicit destination
    10.
    发明授权
    Instruction and logic for predication and implicit destination 有权

    公开(公告)号：US10884735B2

    公开(公告)日：2021-01-05

    申请号：US15905623

    申请日：2018-02-26

    Applicant: Intel Corporation

    Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

    IPC: G06F9/30

    Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

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