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    Ramping inhibit voltage during memory programming
    1.
    发明授权
    Ramping inhibit voltage during memory programming 有权

    公开(公告)号：US10658053B2

    公开(公告)日：2020-05-19

    申请号：US15715980

    申请日：2017-09-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

    Program VT spread folding for NAND flash memory programming
    4.
    发明授权
    Program VT spread folding for NAND flash memory programming 有权
    用于NAND闪存编程的程序VT扩展折叠

    公开(公告)号：US09099183B2

    公开(公告)日：2015-08-04

    申请号：US14139219

    申请日：2013-12-23

    Applicant: Intel Corporation

    Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

    CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

    Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

    Abstract translation: 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。

    Defect management policies for NAND flash memory
    5.
    发明授权
    Defect management policies for NAND flash memory 有权
    NAND闪存的缺陷管理策略

    公开(公告)号：US09535777B2

    公开(公告)日：2017-01-03

    申请号：US14087282

    申请日：2013-11-22

    Applicant: Intel Corporation

    Inventor： Pranav Kalavade ,  Feng Zhu ,  Shyam Sunder Raghunathan ,  Ravi H. Motwani

    IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07 ,  G11B20/18

    CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1012 ,  G11B20/1816

    Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

    Abstract translation: 管理非易失性存储系统中的缺陷的系统和方法，可用于避免无意中丢失数据，同时尽可能保持非易失性存储系统中有用的内存。 所公开的系统和方法可以监视多个触发事件，用于检测非易失性存储系统中包括的一个或多个非易失性存储器（NVM）设备中的可能缺陷，并且基于类型向相应的NVM设备应用一个或多个缺陷管理策略 的触发事件导致检测到可能的缺陷。 可以主动地使用这种缺陷管理策略来以更小的粒度来在非易失性存储系统中退出内存，将存储器的退出重点集中在可能包含缺陷的非易失性存储器的区域上。

    Multi-pulse programming for memory
    7.
    发明授权
    Multi-pulse programming for memory 有权
    多脉冲编程用于存储器

    公开(公告)号：US09245645B2

    公开(公告)日：2016-01-26

    申请号：US13963629

    申请日：2013-08-09

    Applicant: INTEL CORPORATION

    Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

    Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例包括用于存储器件的多脉冲编程的技术和配置。 在一个实施例中，一种方法包括应用多个脉冲来对存储器件的一个或多个多电平单元（MLC）进行编程，其中多个脉冲的各个脉冲与一个或多个MLC的各个级别对应，并且在施加多个 脉冲，验证一个或多个MLC的各个级别的编程。 可以描述和/或要求保护其他实施例。

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