公开(公告)号：US09672102B2

公开(公告)日：2017-06-06

申请号：US14314663

申请日：2014-06-25

Applicant: Intel Corporation

Inventor： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2029/0411

Abstract: Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method includes applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method also includes determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.

公开(公告)号：US09471488B2

公开(公告)日：2016-10-18

申请号：US14961424

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G06F12/02 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/14 ,  G11C5/14 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

公开(公告)号：US09208888B1

公开(公告)日：2015-12-08

申请号：US14318572

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Charan Srinivasan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30 ,  G11C16/14 ,  G11C5/14 ,  G11C11/16 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了提高闪存系统中部分写入的存储块的可靠性和/或性能的方法和装置。 在一些实施例中，存储设备存储对应于在非易失性存储器的部分编程的存储器块上执行的部分写入操作的信息。 至少部分地基于所存储的信息，存储器控制器逻辑然后在对非易失性存储器的读取或写入操作期间使非常易失性存储器的部分的减小的电压电平和/或偏移值应用于非易失性存储器。 还公开并要求保护其他实施例。

公开(公告)号：US09245645B2

公开(公告)日：2016-01-26

申请号：US13963629

申请日：2013-08-09

Applicant: INTEL CORPORATION

Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例包括用于存储器件的多脉冲编程的技术和配置。 在一个实施例中，一种方法包括应用多个脉冲来对存储器件的一个或多个多电平单元（MLC）进行编程，其中多个脉冲的各个脉冲与一个或多个MLC的各个级别对应，并且在施加多个 脉冲，验证一个或多个MLC的各个级别的编程。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09099183B2

公开(公告)日：2015-08-04

申请号：US14139219

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

Abstract translation: 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。