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    Methods for Forming Resistive-Switching Metal Oxides for Nonvolatile Memory Elements
    3.
    发明申请
    Methods for Forming Resistive-Switching Metal Oxides for Nonvolatile Memory Elements 有权
    用于形成用于非易失性存储元件的电阻式开关金属氧化物的方法

    公开(公告)号：US20130109149A1

    公开(公告)日：2013-05-02

    申请号：US13725574

    申请日：2012-12-21

    Applicant: Intermolecular Inc.

    Inventor： Sean Barstow ,  Tony P. Chiang ,  Pragati KUMAR ,  Sandra G. Malhotra

    IPC: H01L45/00

    CPC classification number: H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

    Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以由电阻式开关金属氧化物层形成。 金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。 掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。 基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。 可以选择掺杂剂的离子半径和金属的离子半径彼此接近。 可以对电阻式开关金属氧化物进行退火和氧化操作。 可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

    Titanium-Based High-K Dielectric Films
    4.
    发明申请
    Titanium-Based High-K Dielectric Films 有权
    钛基高K介电薄膜

    公开(公告)号：US20130044404A1

    公开(公告)日：2013-02-21

    申请号：US13657782

    申请日：2012-10-22

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati KUMAR ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

    IPC: H01G4/30 ,  H01G4/018

    CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

    Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

    Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺形成金属 - 绝缘体 - 金属（MIM）堆叠，以形成使用含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

    Reduction of forming voltage in semiconductor devices
    6.
    发明申请
    Reduction of forming voltage in semiconductor devices 有权
    降低半导体器件中的形成电压

    公开(公告)号：US20140001431A1

    公开(公告)日：2014-01-02

    申请号：US14018719

    申请日：2013-09-05

    Applicant: Intermolecular Inc.

    Inventor： Pragati KUMAR ,  Tony P. Chiang ,  Prashant B. Phatak ,  Yun Wang

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

    Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

    Abstract translation: 本公开提供了一种非易失性存储器件及相关的制造和操作方法。 该装置可以包括一个或多个电阻随机存取存储器（ReRAM）方法来为存储器装置提供更可预测的操作。 特别地，可以通过使用阻挡层，反极性形成电压脉冲，从下功函电极注入电子的形成电压脉冲或还原环境中的退火来降低特定设计所需的形成电压 。 可以根据期望的应用和结果应用这些技术中的一种或多种。

    ALD processing techniques for forming non-volatile resistive switching memories
    7.
    发明申请
    ALD processing techniques for forming non-volatile resistive switching memories 有权
    用于形成非易失性电阻式开关存储器的ALD处理技术

    公开(公告)号：US20130273707A1

    公开(公告)日：2013-10-17

    申请号：US13911929

    申请日：2013-06-06

    Applicant: Intermolecular Inc.

    Inventor： Nobumichi Fuchigami ,  Pragati KUMAR ,  Prashant B. Phatak

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

    Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

    Abstract translation: 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

    Resistive-Switching Nonvolatile Memory Elements
    8.
    发明申请
    Resistive-Switching Nonvolatile Memory Elements 有权
    电阻式开关非易失性存储元件

    公开(公告)号：US20130217200A1

    公开(公告)日：2013-08-22

    申请号：US13829378

    申请日：2013-03-14

    Applicant: Intermolecular Inc.

    Inventor： Pragati KUMAR ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G. Malhotra

    IPC: H01L45/00

    CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

    Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

    Inexpensive electrode materials to facilitate rutile phase titanium oxide
    9.
    发明申请
    Inexpensive electrode materials to facilitate rutile phase titanium oxide 审中-公开

    公开(公告)号：US20130037913A1

    公开(公告)日：2013-02-14

    申请号：US13655653

    申请日：2012-10-19

    Applicant: INTERMOLECULAR INC.

    Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati KUMAR ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L29/02

    CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

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