公开(公告)号：US20230163167A1

公开(公告)日：2023-05-25

申请号：US17990142

申请日：2022-11-18

Applicant: Infineon Technologies AG

Inventor： Michael HELL ,  Thomas Aichinger ,  Rudolf Elpelt ,  Caspar Leendertz

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L29/1608 ,  H01L29/1095 ,  H01L29/7813 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/66068

Abstract: A semiconductor device is provided. In an example, the semiconductor device includes a trench gate structure in a silicon carbide (SiC) semiconductor body. The semiconductor device includes a source region of a first conductivity type that adjoins the trench gate structure in a first segment. The semiconductor device includes a semiconductor region of a second conductivity type. The semiconductor region includes a first sub-region arranged below the source region in the first segment, and a second sub-region arranged in a second segment that adjoins the first segment. The semiconductor device includes a current spread region of the first conductivity type. The current spread region includes a first sub-region that adjoins the trench gate structure in the first segment at a vertical distance to a first surface of the SiC semiconductor body, and a second sub-region that is spaced from the trench gate structure in the second segment at the vertical distance to the first surface by a lateral distance.

公开(公告)号：US20250056869A1

公开(公告)日：2025-02-13

申请号：US18799436

申请日：2024-08-09

Applicant: Infineon Technologies AG

Inventor： Fabian RASINGER ,  Michael HELL ,  Thomas AICHINGER ,  Alexey MIKHAYLOV

IPC: H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/423

Abstract: A wide band gap semiconductor device is proposed. The wide band gap semiconductor device includes a wide band gap semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. A gate electrode structure is arranged in an active transistor area. The gate electrode structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the wide band gap semiconductor body. A gate interconnection structure is arranged outside of the active transistor area. The gate interconnection structure includes an interconnection electrode and an interconnection dielectric arranged between the interconnection electrode and the wide band gap semiconductor body. Dielectric constants of a main dielectric component of at least two of i) a part of the gate interconnection dielectric, or ii) a first part of the gate dielectric, or iii) a second part of the gate dielectric differ from one another.

公开(公告)号：US20210193435A1

公开(公告)日：2021-06-24

申请号：US17127309

申请日：2020-12-18

Applicant: Infineon Technologies AG

Inventor： Moriz JELINEK ,  Michael HELL ,  Caspar LEENDERTZ ,  Kristijan Luka MLETSCHNIG ,  Hans-Joachim SCHULZE

IPC: H01J37/317 ,  H01L21/265

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

公开(公告)号：US20250089323A1

公开(公告)日：2025-03-13

申请号：US18827272

申请日：2024-09-06

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Dethard PETERS ,  Michael HELL ,  Andreas HÜRNER

IPC: H01L29/16 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

公开(公告)号：US20250015148A1

公开(公告)日：2025-01-09

申请号：US18764822

申请日：2024-07-05

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Wolfgang BERGNER ,  Hans WEBER ,  Michael HELL ,  Armin TILKE ,  Grazvydas ZIEMYS

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

公开(公告)号：US20250089343A1

公开(公告)日：2025-03-13

申请号：US18824073

申请日：2024-09-04

Applicant: Infineon Technologies AG

Inventor： Andreas HÜRNER ,  Michael HELL ,  Thomas AICHINGER

IPC: H01L29/51 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A power semiconductor device is proposed. The power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising transistor cells. Each of the transistor cells includes a gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes a first gate dielectric layer adjoining to the SiC semiconductor body. The gate dielectric structure further includes a second gate dielectric layer. The gate dielectric structure further includes charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US20240145247A1

公开(公告)日：2024-05-02

申请号：US18407587

申请日：2024-01-09

Applicant: Infineon Technologies AG

Inventor： Moriz JELINEK ,  Michael HELL ,  Caspar LEENDERTZ ,  Kristijan Luka MLETSCHNIG ,  Hans-Joachim SCHULZE

IPC: H01L21/265 ,  H01J37/317 ,  H01L21/04 ,  H01L29/36

CPC classification number: H01L21/26586 ,  H01J37/3171 ,  H01L21/046 ,  H01L21/047 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/36 ,  H01J2237/24578 ,  H01J2237/31703

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.