公开(公告)号：US20250113592A1

公开(公告)日：2025-04-03

申请号：US18374895

申请日：2023-09-29

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Fabian RASINGER ,  Kristijan Luka MLETSCHNIG ,  Romain ESTEVE ,  Caspar LEENDERTZ

IPC: H01L27/07 ,  H01L29/423 ,  H01L29/78 ,  H01L29/872

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor body including a first doped region of a first conductivity type and a second doped region of a second conductivity type. The semiconductor device may include a metal structure, in the semiconductor body, overlying the second doped region. The metal structure may include a first sidewall adjacent a first portion of the first doped region, a second sidewall adjacent a second portion of the first doped region, and a third sidewall adjacent the second doped region. The semiconductor device may include a Schottky contact including a junction of the third sidewall of the metal structure with the second doped region.

公开(公告)号：US20250056869A1

公开(公告)日：2025-02-13

申请号：US18799436

申请日：2024-08-09

Applicant: Infineon Technologies AG

Inventor： Fabian RASINGER ,  Michael HELL ,  Thomas AICHINGER ,  Alexey MIKHAYLOV

IPC: H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/423

Abstract: A wide band gap semiconductor device is proposed. The wide band gap semiconductor device includes a wide band gap semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. A gate electrode structure is arranged in an active transistor area. The gate electrode structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the wide band gap semiconductor body. A gate interconnection structure is arranged outside of the active transistor area. The gate interconnection structure includes an interconnection electrode and an interconnection dielectric arranged between the interconnection electrode and the wide band gap semiconductor body. Dielectric constants of a main dielectric component of at least two of i) a part of the gate interconnection dielectric, or ii) a first part of the gate dielectric, or iii) a second part of the gate dielectric differ from one another.

公开(公告)号：US20250006814A1

公开(公告)日：2025-01-02

申请号：US18756389

申请日：2024-06-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang LEHNERT ,  Fabian RASINGER ,  Thomas AICHINGER ,  Gerald RESCHER ,  Francisco Javier SANTOS RODRIGUEZ ,  Carsten SCHAEFFER ,  Armin TILKE

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

Abstract: A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.