公开(公告)号：US11741030B2

公开(公告)日：2023-08-29

申请号：US17134242

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L45/74 ,  G06F8/73 ,  H04L12/46

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  H04L9/0662 ,  H04L49/15 ,  G06F8/73 ,  G06F13/4273 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L12/4641 ,  H04L45/74 ,  Y02D10/00 ,  Y02D30/00

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20190391939A1

公开(公告)日：2019-12-26

申请号：US16285035

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0808 ,  H04L9/06 ,  G06F13/42 ,  G06F11/10 ,  G06F13/40 ,  G06F1/3287 ,  G06F9/445 ,  G06F9/46 ,  G06F12/0831 ,  G06F12/0806 ,  G06F9/30 ,  G06F8/77 ,  G06F8/71 ,  G06F12/0815 ,  G06F12/0813 ,  H04L12/933

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US20210117350A1

公开(公告)日：2021-04-22

申请号：US17134242

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L12/933 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US09667628B2

公开(公告)日：2017-05-30

申请号：US14534305

申请日：2014-11-06

Applicant: Intel Corporation

Inventor： Simon P. Johnson ,  Asher M. Altman ,  Abhishek Das ,  Vincent R. Scarlata

IPC: H04L29/06 ,  G06F21/51 ,  G06F21/53 ,  G06F21/60

CPC classification number: H04L63/0876 ,  G06F21/51 ,  G06F21/53 ,  G06F21/57 ,  G06F21/60 ,  H04L63/061 ,  H04L63/08

Abstract: The present application is directed to establishing ownership of a secure workspace (SW). A client device may provide a SW data structure (SWDS) to a SW configurator. A SWDS may comprise a hash of an original SW and a public key, and may be signed by a private key corresponding to the public key. The SW configurator may cause an execution container (EC) to be generated including a SW initiated using the SWDS. The client device may claim SW ownership using a request (signed by the private key) transmitted along with a copy of the public key. SW ownership may be determined by an ownership determination module that verifies the signature of the request using the public key received with the request, determines a hash of the received public key and compares the hash of the received public key to a hash of the public key in the SWDS.

公开(公告)号：US12197357B2

公开(公告)日：2025-01-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20240012772A1

公开(公告)日：2024-01-11

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

CPC classification number: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/4286 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F13/4221 ,  G06F12/0806 ,  G06F12/0833 ,  G06F9/466 ,  G06F13/4022 ,  G06F9/44505 ,  G06F13/4282 ,  G06F1/3287 ,  G06F13/4068 ,  G06F11/1004 ,  G06F13/4291 ,  H04L9/0662 ,  G06F12/0808 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US09626321B2

公开(公告)日：2017-04-18

申请号：US14060191

申请日：2013-10-22

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/40 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0815 ,  H04L12/741 ,  G06F9/44

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US12189550B2

公开(公告)日：2025-01-07

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20220114122A1

公开(公告)日：2022-04-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.