公开(公告)号：US20190280188A1

公开(公告)日：2019-09-12

申请号：US16348364

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Justin BROCKMAN ,  Christopher WIEGAND ,  MD Tofizur RAHMAN ,  Daniel OUELETTE ,  Angeline SMITH ,  Juan ALZATE VINASCO ,  Charles KUO ,  Mark DOCZY ,  Kaan OGUZ ,  Kevin O'BRIEN ,  Brian DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

公开(公告)号：US20200303381A1

公开(公告)日：2020-09-24

申请号：US16357221

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Elijah KARPOV ,  Brian DOYLE ,  Abhishek SHARMA ,  Prashant MAJHI ,  Pulkit JAIN

IPC: H01L27/11 ,  H01L49/02 ,  H05K1/18

Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066511A1

公开(公告)日：2020-02-27

申请号：US16113159

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Ilya KARPOV ,  Brian DOYLE ,  Prashant MAJHI ,  Abhishek SHARMA ,  Ravi PILLARISETTY

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/12 ,  C23C14/08 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.