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    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL
    2.
    发明申请
    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL 审中-公开

    公开(公告)号：US20180253377A1

    公开(公告)日：2018-09-06

    申请号：US15755414

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Cunming LIANG ,  Edwin VERPLANK ,  David E. COHEN ,  Danny ZHOU

    IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

    CPC classification number: G06F12/0802 ,  G06F13/20 ,  G06F21/85 ,  G06F2213/0026

    Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

    ADAPTIVE PIPELINE SELECTION FOR ACCELERATING MEMORY COPY OPERATIONS
    3.
    发明申请
    ADAPTIVE PIPELINE SELECTION FOR ACCELERATING MEMORY COPY OPERATIONS 有权

    公开(公告)号：US20220179805A1

    公开(公告)日：2022-06-09

    申请号：US17441668

    申请日：2019-06-21

    Applicant: Intel Corporation

    Inventor： Jiayu HU ,  Ren WANG ,  Cunming LIANG

    IPC: G06F13/16 ,  G06F13/28 ,  G06F9/30

    Abstract: Examples include a computing system having a direct memory access (DMA) engine pipeline, a plurality of processing cores, each processing core including a core pipeline, and a memory coupled to the DMA engine pipeline and the plurality of processing cores. The computing system includes a pipeline selector coupled to the plurality of processing cores and the DMA engine pipeline, the pipeline selector to, during initialization, determine at least one threshold for pipeline selection for the computing system, and during runtime, select one of the core pipelines or the DMA engine pipeline to execute a memory copy operation in the memory based at least in part on the at least one threshold.

    POOLING OF NETWORK PROCESSING RESOURCES
    4.
    发明申请
    POOLING OF NETWORK PROCESSING RESOURCES 有权

    公开(公告)号：US20210266253A1

    公开(公告)日：2021-08-26

    申请号：US17239329

    申请日：2021-04-23

    Applicant: Intel Corporation

    Inventor： Shaopeng HE ,  Haitao KANG ,  Cunming LIANG ,  Anjali Singhai JAIN ,  Parthasarathy SARANGAM ,  Yadong LI

    IPC: H04L12/721 ,  H04L12/741 ,  H04L12/707 ,  H04L12/803 ,  H04L29/06 ,  H04L12/46

    Abstract: Examples described herein relate to a switch configured to allocate packet processing resources, from a pool of packet processing resources, to multiple applications, wherein the pool of packet processing resources comprise configurable packet processing pipelines of one or more network devices and packet processing resources of one or more servers. In some examples, the configurable packet processing pipelines and the packet processing resources are to perform one or more of: network switch operations, microservice communications, and/or block storage operations. In some examples, the network switch operations comprise one or more of: application of at least one access control list (ACL), packet forwarding, packet routing, and/or Virtual Extensible LAN (VXLAN) or GENEVE termination. In some examples, the microservice communications comprise one or more of: packet routing between microservices and/or load balancing of utilized microservices.

    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL
    7.
    发明申请
    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL 有权

    公开(公告)号：US20210216453A1

    公开(公告)日：2021-07-15

    申请号：US17216462

    申请日：2021-03-29

    Applicant: Intel Corporation

    Inventor： Cunming LIANG ,  Edwin VERPLANKE ,  David E. COHEN ,  Danny Yigang ZHOU

    IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

    Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL
    8.
    发明申请
    SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL 审中-公开

    公开(公告)号：US20190243757A1

    公开(公告)日：2019-08-08

    申请号：US16387223

    申请日：2019-04-17

    Applicant: Intel Corporation

    Inventor： Cunming LIANG ,  Edwin VERPLANKE ,  David E. COHEN ,  Danny ZHOU

    IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

    CPC classification number: G06F12/0802 ,  G06F13/20 ,  G06F21/85 ,  G06F2213/0026

    Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

    Apparatuses, Devices, Methods and Computer Programs for Modifying a Target Application
    9.
    发明公开
    Apparatuses, Devices, Methods and Computer Programs for Modifying a Target Application 审中-公开

    公开(公告)号：US20240103842A1

    公开(公告)日：2024-03-28

    申请号：US18528921

    申请日：2023-12-05

    Applicant: Intel Corporation

    Inventor： Cunming LIANG ,  Ping YU ,  Zongmin GU

    IPC: G06F8/65

    CPC classification number: G06F8/65

    Abstract: Examples relate to apparatuses, devices, methods and computer programs for modifying a target application. An apparatus for a computer system comprises memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to launch, using a loader application, a target application, obtain, by the loader application, information on a kernel system call having been made by the target application, and modify, by the loader application and based on the information on the kernel system call having been made by the target application, an instruction of the target application, wherein the modified instruction is configured to trigger an operation being equivalent to the kernel system call, with the operation being equivalent to the kernel system call while avoiding a context switch.

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