公开(公告)号：US20220413591A1

公开(公告)日：2022-12-29

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. SHAH ,  Suresh CHEMUDUPATI ,  Alexander GENDLER ,  David HUNT ,  Christopher M. MACNAMARA ,  Ofer NATHAN ,  Adwait PURANDARE ,  Ankush VARMA

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

公开(公告)号：US20230353508A1

公开(公告)日：2023-11-02

申请号：US18220206

申请日：2023-07-10

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Patrick CONNOR ,  Scott P. DUBAL ,  James R. HEARN ,  Brendan RYAN ,  Chris MACNAMARA ,  Conor WALSH ,  David HUNT ,  John J. BROWNE ,  Kevin LAATZ

IPC: H04L49/00 ,  H04L47/625

CPC classification number: H04L49/3018 ,  H04L47/626

Abstract: Examples described herein relate to a system within a package. In some examples, the system includes a communication fabric and circuitry to adjust a packet throughput rate associated with the communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage. In some examples, the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator, a processor, a memory, or a network interface device.

公开(公告)号：US20190052530A1

公开(公告)日：2019-02-14

申请号：US16160176

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Mohammad Abdul AWAL ,  Jasvinder SINGH ,  Reshma PATTAN ,  David HUNT ,  Declan DOHERTY ,  Chris MACNAMARA

IPC: H04L12/24 ,  H04L12/26 ,  H04L12/861

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

公开(公告)号：US20230035142A1

公开(公告)日：2023-02-02

申请号：US17966441

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  David HUNT ,  Kevin LAATZ ,  Anatoly BURAKOV ,  Bruce RICHARDSON ,  Conor WALSH ,  John J. BROWNE

IPC: G06F9/50

Abstract: A method is described. The method includes polling a queue a plurality of times over a plurality of intervals, where, the queue feeds work items to a processor. The method includes determining, from the polling, respective work item flow metrics for the plurality of intervals. The method includes determining a processor's performance setting based on the plurality of respective work item flow metrics.

公开(公告)号：US20230027516A1

公开(公告)日：2023-01-26

申请号：US17957723

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Tomasz KANTECKI ,  Paul HOUGH ,  David CREMINS ,  Ciara LOFTUS ,  Aman Deep SINGH ,  John J. BROWNE ,  David HUNT ,  Maksim LUKOSHKOV ,  Amruta MISRA ,  Nirint SHAH ,  Chris MACNAMARA

IPC: G06F13/14 ,  H04L1/18

Abstract: A processor-to-processor agent to provide connectivity over a processor-to-processor interconnect between services/network functions on different processors on a same compute node in a server is provided. The processor-to-processor agent can intercept socket interface calls using a network traffic filter in the network stack and redirect the packets based on traffic matching rules.

公开(公告)号：US20250013493A1

公开(公告)日：2025-01-09

申请号：US18889249

申请日：2024-09-18

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  John J. BROWNE ,  Nilanjan PALIT ,  Chetan HIREMATH ,  Rory SEXTON ,  Conor WALSH ,  Kevin LAATZ ,  Andriy GLUSTSOV ,  Peter McCARTHY ,  Katelyn DONNELLAN ,  Vishal DEEP AJMERA ,  David HUNT ,  Gordon NOONAN

IPC: G06F9/48

Abstract: Examples described herein relate to circuitry to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust a frequency of operation of the interface circuitry based on the monitored utilization data and the determined priority levels of the processes. In some examples, adjust the frequency of operation of the interface circuitry is to prioritize frequency of operation requested by a higher priority workload over a frequency of operations requested by a lower priority workload.

公开(公告)号：US20220155847A1

公开(公告)日：2022-05-19

申请号：US17559170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Konstantin ANANYEV ,  Anatoly BURAKOV ,  David HUNT ,  Chris MACNAMARA ,  Edwin VERPLANKE ,  Omkar MASLEKAR ,  Gilbert NEIGER ,  Rajesh M. SANKARAN

IPC: G06F1/3296 ,  G06F3/06

Abstract: Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.

公开(公告)号：US20210157626A1

公开(公告)日：2021-05-27

申请号：US17165694

申请日：2021-02-02

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  Chris MACNAMARA ,  John J. BROWNE ,  Liang MA ,  Shobhi JAIN ,  David HUNT

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/4401 ,  H04L12/24

Abstract: Examples described herein relate to circuitry to boot a virtualized execution environment (VEE) by use of system resources, wherein the system resources are allocated based on a priority level of the VEE. In some examples, the circuitry to boot a VEE by use of system resources is to access an identification of system resources to use to boot the VEE and priority level of the VEE from stored data. In some examples, the priority level of the VEE is based on a service level agreement (SLA), service level objective (SLO), or class of service (COS) that identifies boot time of the VEE. In some examples, the circuitry is to boot a VEE by use of system resources, wherein the system resources are allocated based on a priority level of the VEE and also based on a number of VEEs that boot concurrently.

公开(公告)号：US20200225724A1

公开(公告)日：2020-07-16

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  John J. BROWNE ,  Tomasz KANTECKI ,  David HUNT ,  Anatoly BURAKOV ,  Srihari MAKINENI ,  Nikhil GUPTA ,  Ankush VARMA ,  Dorit SHAPIRA ,  Vasudevan SRINIVASAN ,  Bryan T. BUTTERS ,  Shrikant M. SHAH

IPC: G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/20

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).