公开(公告)号：US20230299123A1

公开(公告)日：2023-09-21

申请号：US17698939

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Gwang-Soo Kim ,  Said Rami

IPC: H01L49/02 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L28/10 ,  H01L24/08 ,  H01L23/5227 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0613 ,  H01L25/0652

Abstract: In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

公开(公告)号：US20230207525A1

公开(公告)日：2023-06-29

申请号：US17561845

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sriram Srinivasan ,  Christopher Pelto ,  Gwang-Soo Kim ,  Nitin Deshpande ,  Omkar Karhade

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06568

Abstract: A packaged device comprises first die stack and a third die. The first die stack includes a first die comprising first conductive contacts each at a first side of the first die, and a second die comprising second conductive contacts each at a second side of the second die. First solder bonds which each extend to a respective one of the first conductive contacts. The third die comprises third conductive contacts each at a third side of the third die. The third die is coupled to the first die stack via second solder bonds which each extend to a respective one of the second conductive contacts, and to a respective one of the third conductive contacts. Each die of the first die stack is coupled to each of a respective one or more other dies of the first die stack via respective hybrid bonds.

公开(公告)号：US20230197637A1

公开(公告)日：2023-06-22

申请号：US17554471

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mohammad Enamul Kabir ,  Nitin Deshpande ,  Omkar Karhade ,  Arnab Sarkar ,  Sairam Agraharam ,  Christopher Pelto ,  Gwang-Soo Kim ,  Ravindranath Mahajan

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L23/564 ,  H01L25/0655 ,  H01L21/447

Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

公开(公告)号：US11444148B2

公开(公告)日：2022-09-13

申请号：US16222253

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Aaron D. Lilak ,  Kumhyo Byon ,  Doug Ingerly

IPC: H01L49/02 ,  H01F29/14 ,  H01L21/768 ,  H01F27/29 ,  H01F27/28 ,  H01F41/04 ,  H01L27/06

Abstract: An inductor is disclosed. The inductor includes a vertically coiled conductor, a metal contact coupled to a first end of the vertically coiled conductor, and a dielectric material coupled to the metal contact. A tunable high permittivity component is coupled to a second end of the vertically coiled conductor.

公开(公告)号：US20230207486A1

公开(公告)日：2023-06-29

申请号：US17561833

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Dimitrios Antartis ,  Han Ju Lee ,  Christopher Pelto

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76802 ,  H01L21/76877

Abstract: An integrated circuit (IC) die comprises a first metallization layer comprising first interconnect structures which each extend through the first metallization layer, a second metallization layer comprising second interconnect structures which each extend through the second metallization layer, an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer. The ILD stack comprises a stress modulation layer on the first metallization layer and a capping layer on the stress modulation layer. A first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer.

公开(公告)号：US10811354B2

公开(公告)日：2020-10-20

申请号：US16306538

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Doug B. Ingerly

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/62

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112168A1

公开(公告)日：2025-04-03

申请号：US18477813

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Gwang-Soo Kim ,  Harini Kilambi ,  Han Ju Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: Alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. The alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. A reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. The alignment markers can further be used to align a wafer bonding layer to the reconstituted wafer. The wafer bonding layer can be used in attaching the reconstituted wafer to an interposer, another wafer, or another microelectronic structure. The alignment markers are located outside an outer lateral boundary of the integrated circuit dies (such as between integrated circuit dies) and are not connected to any metal lines in the integrated circuit dies in the reconstituted wafer.

公开(公告)号：US20250105207A1

公开(公告)日：2025-03-27

申请号：US18473046

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Ashok Deshpande ,  Dimitrios Antartis ,  Gwang-Soo Kim ,  Shawna Marie Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Systems, apparatus, and articles of manufacture are disclosed to enable integrated circuit packages with double hybrid bonded dies and methods of manufacturing the same include an integrated circuit (IC) package including a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, a second semiconductor die including second metal pads of the second semiconductor die, and a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads, a first one of the third metal vias positioned beyond a lateral side of the first semiconductor die.