公开(公告)号：US20210280463A1

公开(公告)日：2021-09-09

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US12002727B2

公开(公告)日：2024-06-04

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/3185 ,  H01L23/3675 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/35121

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US20210289638A1

公开(公告)日：2021-09-16

申请号：US17336008

申请日：2021-06-01

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US11528811B2

公开(公告)日：2022-12-13

申请号：US17336008

申请日：2021-06-01

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US20200236795A1

公开(公告)日：2020-07-23

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H05K5/00 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US20240006327A1

公开(公告)日：2024-01-04

申请号：US17856663

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert A. May ,  Brandon Marin ,  Benjamin Duong ,  Suddhasattwa Nad ,  Hsin-Wei Wang ,  Leonel Arana ,  Darko Grujicic

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/08

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

公开(公告)号：US11116084B2

公开(公告)日：2021-09-07

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US10515824B2

公开(公告)日：2019-12-24

申请号：US15868942

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Leonel Arana ,  Nicholas S. Haehn ,  Hsin-Wei Wang ,  Oscar Ojeda ,  Arnab Roy

IPC: H01L21/321 ,  H01L21/3213 ,  C23F1/14 ,  H01L21/48

Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

公开(公告)号：US11817349B2

公开(公告)日：2023-11-14

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76885 ,  H01L21/7685 ,  H01L21/76834 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/53238 ,  H01L21/32134

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US20220199453A1

公开(公告)日：2022-06-23

申请号：US17132372

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael J. Baker ,  Shawna M. Liff ,  Hsin-Wei Wang ,  Albert S. Lopez

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.