公开(公告)号：US20210249322A1

公开(公告)日：2021-08-12

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US12130482B2

公开(公告)日：2024-10-29

申请号：US17132851

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bassam Ziadeh ,  Jingyi Huang ,  Yiqun Bai ,  Ziyin Lin ,  Vipul Mehta ,  Joseph Van Nausdle

IPC: G02B6/42

CPC classification number: G02B6/4239 ,  G02B6/4212 ,  G02B6/423 ,  G02B6/426

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US11688634B2

公开(公告)日：2023-06-27

申请号：US16526012

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Vipul Mehta ,  Yiqun Bai ,  Ziyin Lin ,  John Decker ,  Yan Li

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L21/76877 ,  H01L21/565 ,  H01L21/76804 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.

公开(公告)号：US11749585B2

公开(公告)日：2023-09-05

申请号：US16805392

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Vipul Mehta ,  John Decker ,  Ziyin Lin

IPC: H01L23/31 ,  H01L23/433 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/4334 ,  H01L21/56 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/50

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

公开(公告)号：US11676876B2

公开(公告)日：2023-06-13

申请号：US16557891

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Elizabeth Nofen ,  Vipul Mehta ,  Taylor Gaines

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/367 ,  H01L23/373 ,  H01L21/67

CPC classification number: H01L23/3178 ,  H01L21/565 ,  H01L21/67288 ,  H01L23/367 ,  H01L23/373

Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20210272878A1

公开(公告)日：2021-09-02

申请号：US16805392

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Vipul Mehta ,  John Decker ,  Ziyin Lin

IPC: H01L23/433 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

公开(公告)号：US12002727B2

公开(公告)日：2024-06-04

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/3185 ,  H01L23/3675 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/35121

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US11776821B2

公开(公告)日：2023-10-03

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L21/563 ,  H01L21/67126 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/564 ,  H05K2201/09045

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

公开(公告)号：US11282717B2

公开(公告)日：2022-03-22

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.