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    PHOTONIC INTEGRATED CIRCUIT AND OPTICAL COUPLER DESIGNS FOR IMPROVING PROCESS TOLERANCE
    1.
    发明申请
    PHOTONIC INTEGRATED CIRCUIT AND OPTICAL COUPLER DESIGNS FOR IMPROVING PROCESS TOLERANCE 有权

    公开(公告)号：US20250004220A1

    公开(公告)日：2025-01-02

    申请号：US18346039

    申请日：2023-06-30

    Applicant: Intel Corporation

    Inventor： Sufi R. Ahmed ,  Shan Zhong ,  Eric J. M. Moret ,  Yang Wu

    IPC: G02B6/42

    Abstract: Photonic integrated circuits and optical couplers with improved process tolerance, and methods of forming the same, are disclosed herein. In one example, an integrated circuit package includes a photonic integrated circuit (PIC) to send or receive optical signals and an optical coupler to optically couple the PIC to one or more optical fibers. The PIC includes a first interface with at least two recesses and one or more grooves positioned between the recesses, and the optical coupler includes a second interface with at least two protrusions and one or more ridges positioned between the protrusions (or vice versa). The protrusions on the optical coupler are mated with the recesses on the PIC, and the ridges on the optical coupler are mated with the grooves on the PIC.

    BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT
    2.
    发明申请
    BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT 有权

    公开(公告)号：US20210249322A1

    公开(公告)日：2021-08-12

    申请号：US16788186

    申请日：2020-02-11

    Applicant: INTEL CORPORATION

    Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

    IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00

    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

    Interconnect structures with polymer core
    3.
    发明授权
    Interconnect structures with polymer core 有权

    公开(公告)号：US10128225B2

    公开(公告)日：2018-11-13

    申请号：US15436291

    申请日：2017-02-17

    Applicant: INTEL CORPORATION

    Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

    IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L25/065 ,  H01L23/31

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

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