公开(公告)号：US11973105B2

公开(公告)日：2024-04-30

申请号：US16145111

申请日：2018-09-27

申请人： Intel Corporation

发明人： Chieh-Jen Ku ,  Bernhard Sell ,  Leif Paulson ,  Kinyip Phoa ,  Shi Liu

IPC分类号： H01L23/522 ,  H01L27/01 ,  H01L49/02

CPC分类号： H01L28/24 ,  H01L23/5228 ,  H01L27/016

摘要： An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.

公开(公告)号：US11018264B1

公开(公告)日：2021-05-25

申请号：US16715135

申请日：2019-12-16

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Kinyip Phoa ,  Tahir Ghani ,  Rajesh Kumar

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088

摘要： Described herein are three-dimensional nanoribbon-based logic ICs that include one of more of 1) individual gate control in a vertical stack of nanoribbons, 2) inter-ribbon interconnects in a vertical stack of nanoribbons, and 3) both P- and N-type nanoribbons in a vertical stack of nanoribbons. Using one or more of these features may help realize unique monolithic 3D logic architectures that were not possible with conventional logic circuits and may allow realizing logic devices with favorable metrics in terms of power and performance while preserving the substrate area and cost.

公开(公告)号：US10312367B2

公开(公告)日：2019-06-04

申请号：US15301282

申请日：2014-06-20

申请人： Intel Corporation

发明人： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Ting Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/092

摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

公开(公告)号：US10158034B2

公开(公告)日：2018-12-18

申请号：US15127207

申请日：2014-06-27

申请人： Intel Corporation

发明人： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez ,  Yi Wei Chen

IPC分类号： H01L31/044 ,  H01L31/0224 ,  H01L31/056 ,  H01L31/047 ,  H02S40/38 ,  H01L31/028 ,  H01L31/05 ,  H01L31/068 ,  H01L31/18

摘要： An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

摘要： Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11737362B2

公开(公告)日：2023-08-22

申请号：US16074151

申请日：2016-04-01

申请人： Intel Corporation

发明人： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC分类号： H01L35/14 ,  H10N10/10 ,  H10N10/17 ,  H10N10/81 ,  H10N10/851 ,  H10N19/00 ,  H01L29/78

CPC分类号： H10N10/10 ,  H01L29/785 ,  H10N10/17 ,  H10N10/81 ,  H10N10/851 ,  H10N19/00

摘要： An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.

公开(公告)号：US20220157729A1

公开(公告)日：2022-05-19

申请号：US17649637

申请日：2022-02-01

申请人： Intel Corporation

发明人： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC分类号： H01L23/538 ,  H01L21/768

摘要： An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US11257822B2

公开(公告)日：2022-02-22

申请号：US16691163

申请日：2019-11-21

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

摘要： Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US20170025533A1

公开(公告)日：2017-01-26

申请号：US15301282

申请日：2014-06-20

申请人： Kinyip PHOA ,  Nidhi NIDHI ,  Chia-Hong JAN ,  Ting CHANG ,  INTEL CORPORATION

发明人： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Ting Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7834 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/7835

摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

摘要翻译： 跨越多个非平面半导体器件（例如鳍片或纳米线）的高压晶体管与利用单个非平面半导体器件的非平面晶体管单片集成。 非平面FET可用于IC内的低电压CMOS逻辑电路，而高电压晶体管可用于IC内的高电压电路。 栅极堆叠可以设置在高压通道区域上，该高压通道区域分离一对翅片，其中每个翅片用作高压设备的源极/漏极的一部分。 高压通道区域可以是相对于翅片凹进的基板的平面长度。 高压栅极堆叠可以使用围绕散热片的隔离电介质作为厚栅极电介质。 高压晶体管可以包括形成在衬底中的一对掺杂阱，其被高压栅极堆叠分隔开，其中一个或多个鳍包围在每个阱内。

公开(公告)号：US12058849B2

公开(公告)日：2024-08-06

申请号：US17522225

申请日：2021-11-09

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC分类号： H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

CPC分类号： H10B12/312 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

摘要： Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.