公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11869987B2

公开(公告)日：2024-01-09

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/93 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/66174

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11824116B2

公开(公告)日：2023-11-21

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Ayan Kar ,  Nicholas Thomson ,  Benjamin Orr ,  Nathan Jack ,  Kalyan Kolluru ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7831 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20220415877A1

公开(公告)日：2022-12-29

申请号：US17358934

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Benjamin Orr ,  Rohit Grover ,  Nathan Jack ,  Nicholas Thomson ,  Rui Ma ,  Ayan Kar ,  Kalyan Kolluru

IPC: H01L27/02 ,  H01L27/088

Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.

公开(公告)号：US11652107B2

公开(公告)日：2023-05-16

申请号：US16447874

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Nicholas Thomson ,  Ayan Kar ,  Kalyan Kolluru ,  Nathan Jack ,  Rui Ma ,  Mark Bohr ,  Rishabh Mehandru ,  Halady Arpit Rao

IPC: H01L29/06 ,  H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L29/861

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/1211 ,  H01L29/8613

Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

公开(公告)号：US11417781B2

公开(公告)日：2022-08-16

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.