公开(公告)号：US20170025533A1

公开(公告)日：2017-01-26

申请号：US15301282

申请日：2014-06-20

申请人： Kinyip PHOA ,  Nidhi NIDHI ,  Chia-Hong JAN ,  Ting CHANG ,  INTEL CORPORATION

发明人： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Ting Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7834 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/7835

摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

摘要翻译： 跨越多个非平面半导体器件（例如鳍片或纳米线）的高压晶体管与利用单个非平面半导体器件的非平面晶体管单片集成。 非平面FET可用于IC内的低电压CMOS逻辑电路，而高电压晶体管可用于IC内的高电压电路。 栅极堆叠可以设置在高压通道区域上，该高压通道区域分离一对翅片，其中每个翅片用作高压设备的源极/漏极的一部分。 高压通道区域可以是相对于翅片凹进的基板的平面长度。 高压栅极堆叠可以使用围绕散热片的隔离电介质作为厚栅极电介质。 高压晶体管可以包括形成在衬底中的一对掺杂阱，其被高压栅极堆叠分隔开，其中一个或多个鳍包围在每个阱内。

公开(公告)号：US09570467B2

公开(公告)日：2017-02-14

申请号：US14641117

申请日：2015-03-06

申请人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

摘要翻译： 描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。 例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。 第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。 半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。 第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。 第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

公开(公告)号：US20170005187A1

公开(公告)日：2017-01-05

申请号：US15100286

申请日：2014-01-24

申请人： Walid M. Hafez ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L29/74 ,  H01L29/66 ,  H01L29/417 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

摘要翻译： 公开了半导体器件，集成电路器件和方法的实施例。 在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。 第一翅片可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，第三材料设置在第四材料和第二材料之间。 第一和第三材料可以由第一类型的非本征半导体形成，并且第二和第四材料可以由第二种不同类型的外在半导体形成。 第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一个物质连接。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20150187709A1

公开(公告)日：2015-07-02

申请号：US14142629

申请日：2013-12-27

申请人： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

发明人： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L23/62 ,  H01L21/3205 ,  H01L21/02

CPC分类号： H01L23/62 ,  H01L21/0217 ,  H01L21/32055 ,  H01L23/5256 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。 在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。 隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。 隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140308785A1

公开(公告)日：2014-10-16

申请号：US14313678

申请日：2014-06-24

申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

公开(公告)号：US20110215422A1

公开(公告)日：2011-09-08

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L21/8238 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20100133595A1

公开(公告)日：2010-06-03

申请号：US12700637

申请日：2010-02-04

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US07541239B2

公开(公告)日：2009-06-02

申请号：US11479762

申请日：2006-06-30

申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

IPC分类号： H01L21/8238 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

公开(公告)号：US20090011565A1

公开(公告)日：2009-01-08

申请号：US12231172

申请日：2008-08-28

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US06887762B1

公开(公告)日：2005-05-03

申请号：US09831539

申请日：1999-11-05

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer (108) adjacent to the vertical sidewalls of the gate electrode (106), or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极（106）的垂直侧壁相邻的侧壁间隔物（108）的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分 。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。