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公开(公告)号：US10998302B2
公开(公告)日：2021-05-04
申请号：US16586167
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Adel Elsherbini , Van Le , Johanna Swan , Shawna Liff , Patrick Morrow , Gerald Pasdast , Min Huang
IPC: H01L25/18 , G06F13/40 , H01L25/065 , H01L25/00 , H01L23/48 , H01L25/075 , H01L21/768 , H01L25/07 , H01L25/04
Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.
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公开(公告)号：US09405340B2
公开(公告)日：2016-08-02
申请号：US13928724
申请日：2013-06-27
Applicant: Intel Corporation
Inventor： Baskaran Ganesan , Eric Dehaemer , Vinod Ambrose , Harjinder Hullon , Joseph Doucette , Seow Fung Ooi , Min Huang , Zhiguo Wang , Yin-Lung Lu , William Johnson Bowhill
CPC classification number: G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括分组为多个群集的多个核心。 基于在多个频率中的每一个处的每个核心的对应的工作电压来形成簇。 每个集群包括唯一的一组核心，并且至少一个集群包括至少两个核心。 所述处理器还包括功率控制单元（PCU），其响应于对第一集群的第一核心的频率变化请求而包括频率/电压控制逻辑，以从第一集群电压 - 频率（ VF）表与第一个集群关联。 第一簇V-F表在第一簇的核的多个操作频率的每一个上唯一地指定对应的工作电压。 描述和要求保护其他实施例。
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3.发明申请公开(公告)号：US20200091986A1
公开(公告)日：2020-03-19
申请号：US16494474
申请日：2017-04-07
Applicant: Intel Corporation
IPC: H04B7/06 , H04B7/0456 , H04B7/0452
Abstract: The disclosure relates to a radio transceiver, comprising: a precoder configured to precode a data signal for transmission to a plurality of multi-stream terminals based on a plurality of precoding weight matrices; and a processor configured to generate for each terminal in an iterative manner a precoding weight matrix and a transformed channel matrix, wherein the transformed channel matrix indicates a channel gain between the radio transceiver and the respective terminal transformed by a receive filter matrix of the respective terminal, wherein the generation of the precoding weight matrix and the transformed channel matrix in a current iteration is based on the transformed channel matrix generated from a previous iteration.
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公开(公告)号：US10474526B2
公开(公告)日：2019-11-12
申请号：US15282711
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Bahaa Fahim , Min Huang , Zhiguo Wang
IPC: G06F11/10 , G06F12/0811 , G11C29/44 , G11C29/00 , G06F12/0868 , G06F12/0875 , G11C29/52 , G11C29/04
Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.
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公开(公告)号：US20180095823A1
公开(公告)日：2018-04-05
申请号：US15282711
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Bahaa Fahim , Min Huang , Zhiguo Wang
IPC: G06F11/10 , G06F3/06 , G06F12/0811 , G11C29/52
Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.
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Patent Agency Ranking
公开(公告)号：US09335814B2
公开(公告)日：2016-05-10
申请号：US14012362
申请日：2013-08-28
Applicant: Intel Corporation
Inventor： Stefan Rusu , Min Huang , Wei Chen , Krishnakanth V. Sistla
CPC classification number: G06F1/3275 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D50/20
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令;高速缓存存储器，包括分布在处理器的管芯上的多个部分;多个休眠电路，每个休眠电路分别耦合到高速缓冲存储器的一个部分， 以及耦合到所述高速缓存存储器部分的至少一个睡眠控制逻辑，以针对每个所述睡眠电路独立动态地确定睡眠设置，并且使所述相应的休眠电路能够将所述对应的高速缓冲存储器部分维持在保持电压。 描述和要求保护其他实施例。
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7.发明授权公开(公告)号：US11159995B2
公开(公告)日：2021-10-26
申请号：US16083894
申请日：2016-04-14
Applicant: Intel Corporation
IPC: H04W36/30 , H04W36/00 , H04B7/0456 , H04B7/024 , H04B7/0413 , H04B7/06 , H04W88/08
Abstract: In various aspects, devices and methods for performing a handover in a MIMO system are described herein. According to at least one aspect, a wireless communication device is described to include one or more receivers that measures beams of a neighbor cell in response to a command of a MIMO communication system. In some aspects, the wireless communication device further includes one or more transmitters that reports information of the beams based on the measured beams to the massive MIMO communication system. The information is, in at least one aspect, incorporated in a Beam Specific-Neighbor Cell Relation (BS-NCR).
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公开(公告)号：US20210098440A1
公开(公告)日：2021-04-01
申请号：US16586167
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Adel Elsherbini , Van Le , Johanna Swan , Shawna Liff , Patrick Morrow , Gerald Pasdast , Min Huang
IPC: H01L25/18 , G06F13/40 , H01L25/065 , H01L25/00
Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.
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公开(公告)号：US20200178326A1
公开(公告)日：2020-06-04
申请号：US16615081
申请日：2018-06-19
Applicant: Intel Corporation
Inventor： Alexander Sirotkin , Yifan Yu , Min Huang , Jaemin Han , Feng Yang
IPC: H04W76/12
Abstract: Embodiments of a Next Generation Node B (gNB) are described herein. The gNB may be configured with logical nodes, including a gNB central unit (gNB-CU) and a gNB distributed unit (gNB-DU). The gNB-CU may comprise a gNB-CU control plane (gNB-CU-CP) for control-plane functionality, and a gNB-CU user plane (gNB-CU-UP) for user-plane functionality. The gNB may initiate an E1 interface setup procedure, a bearer context setup procedure, and a UE context setup procedure to establish a UE context that includes a signaling radio bearer (SRB) and a data radio bearer (DRB) configuration. The UE context setup request message may be configured to include quality-of-service parameters for the DRB configuration.
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公开(公告)号：US20200029390A1
公开(公告)日：2020-01-23
申请号：US16487173
申请日：2018-03-16
Applicant: Intel Corporation
Inventor： Jaemin Han , Yujian Zhang , Alexander Sirotkin , Xu Zhang , Yifan Yu , Min Huang , Feng Yang , Sudeep Palat
Abstract: A centralized RAN architecture that includes lower layer transmission nodes (referred to as distributed units (DUs) herein) that connect to an upper layer RAN node (referred to as a centralized unit (CU) herein). A centralized RAN architecture may include a functional split, between the CU and DU, corresponding to the Packet Data Convergence Protocol (PDCP) and Radio Link Control (RLC) layers. In one embodiment, a CU may store copies of downlink PDCP PDUs that are transmitted to a first DU. The CU may retransmit, to a second DU, those of the PDCP PDUs which were previously transmitted to the source DU but have not been acknowledged as successfully delivered by the source DU.
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