公开(公告)号：US20250081597A1

公开(公告)日：2025-03-06

申请号：US18240106

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Anindya DASGUPTA ,  Ankit Kirit LAKHANI ,  Guanqun CHEN ,  Ian TOLLE ,  Saurabh ACHARYA ,  Shengsi LIU ,  Baofu ZHU ,  Nikhil MEHTA ,  Krishna GANESAN ,  Charles H. WALLACE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20240105716A1

公开(公告)日：2024-03-28

申请号：US17954206

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Mohit K. HARAN ,  Stephen M. CEA ,  Charles H. WALLACE ,  Tahir GHANI ,  Shengsi LIU ,  Saurabh ACHARYA ,  Thomas O'BRIEN ,  Nidhi KHANDELWAL ,  Marie T. CONTE ,  Prabhjot LUTHRA

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20240429125A1

公开(公告)日：2024-12-26

申请号：US18212382

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Shengsi LIU ,  Saurabh ACHARYA

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having deep via bar isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes has a cut between first and second conductive structure portions. A cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.

公开(公告)号：US20240105803A1

公开(公告)日：2024-03-28

申请号：US17953096

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Dan S. LAVRIC ,  Charles H. WALLACE ,  Tahir GHANI ,  Saurabh ACHARYA ,  Thomas O'BRIEN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78696

Abstract: Integrated circuit structures having trench contact depopulation structures, and methods of fabricating integrated circuit structures having trench contact depopulation structures, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate stack is over the vertical stack of horizontal nanowires. A dielectric trench structure is adjacent to the gate stack. A dielectric sidewall spacer is between the gate stack and the dielectric trench structure. A dielectric gate cut plug is extending through the gate stack, the dielectric sidewall spacer, and the dielectric trench structure.

公开(公告)号：US20250107195A1

公开(公告)日：2025-03-27

申请号：US18373466

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Thomas O’BRIEN ,  Anindya DASGUPTA ,  Shengsi LIU ,  Saurabh ACHARYA ,  Charles H. WALLACE ,  Baofu ZHU

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate structure is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure has a first portion laterally spaced apart from the epitaxial source or drain structure, a second portion vertically over the epitaxial source or drain structure, and a third portion between the first portion and the second portion. A dielectric plug is laterally between the epitaxial source or drain structure and the first portion of the conductive trench contact structure, wherein the third portion of the conductive trench contact structure is vertically over the dielectric plug.

公开(公告)号：US20240105802A1

公开(公告)日：2024-03-28

申请号：US17953085

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Marie CONTE ,  Charles H. WALLACE ,  Robert JOACHIM ,  Shengsi LIU ,  Saurabh ACHARYA ,  Nidhi KHANDELWAL ,  Kyle T. HORAK ,  Robert ROBINSON ,  Brandon PETERS

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78696

Abstract: Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.

公开(公告)号：US20240105774A1

公开(公告)日：2024-03-28

申请号：US17955513

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Jessica PANELLA ,  Saurabh ACHARYA ,  Desalegne B. TEWELDEBRHAN ,  Madeleine BEASLEY

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Integrated circuit structures having uniform epitaxial source or drain cut are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires. A second sub-fin structure is beneath a second stack of nanowires. A first epitaxial source or drain structure is at an end of the first stack of nanowires, the first epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall. A second epitaxial source or drain structure is at an end of the second stack of nanowires, the second epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall, the first lateral sidewall of the second epitaxial source or drain structure laterally spaced apart from the second lateral sidewall of the first epitaxial source or drain structure.