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公开(公告)号：US20160181719A1
公开(公告)日：2016-06-23
申请号：US14578707
申请日：2014-12-22
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , Wayne Genetti , Keith Mease , Mark Wessel
IPC: H01R13/502 , H01R43/20
CPC classification number: H01R13/502 , H01R43/20 , H04L49/40 , H04Q1/15
Abstract: A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.
Abstract translation: 电缆中平面包括沿着连接到有线中平面两侧的线路卡的第一连接器组和第二连接器组之间的平面的第一支撑板。 第一连接器组和第二连接器组包括连接器片。 布线子层包括电缆片，以在第一连接器组件的连接器的第一连接器片与第二连接器组的连接器的第一连接片之间提供连接，使得第一布线子层将每个连接器 的第一连接器组，通过一个电缆片，连接到第二连接器组的连接器。 添加附加的布线子层，并且设置平行于第一支撑板的第二支撑板以包围并支撑第一支撑板和第二支撑板之间的布线子层。 描述其他设备和方法。
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2.发明申请PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD HAVING MULTIPLE PCIe CONNECTORS 有权具有多个PCIe连接器的外围部件互连显式（PCIe）卡公开(公告)号：US20160170928A1
公开(公告)日：2016-06-16
申请号：US14569041
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , Wayne Genetti , David Schweitzer
CPC classification number: G06F13/4282 , G06F1/16 , G06F1/185 , G06F1/186 , G06F13/4022 , G06F13/409 , G06F2213/0026 , H01R12/716 , H01R12/721 , H01R12/722 , H01R12/727 , H01R12/73 , H01R12/737 , H05K1/0296 , H05K1/145 , H05K3/308 , H05K5/0286 , H05K7/1422 , H05K2201/10
Abstract: Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.
Abstract translation: 一些实施例包括具有电路板的装置和方法，位于电路板上的装置，位于电路板上并耦合到该装置的第一外围组件互连Express（PCIe）连接器，以及位于电路板上的第二PCIe连接器 并耦合到该设备。 第一PCIe连接器布置成耦合到附加电路板的第一连接器。 第二PCIe连接器布置成耦合到附加电路板的第二连接器。
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公开(公告)号：US11217573B2
公开(公告)日：2022-01-04
申请号：US16809515
申请日：2020-03-04
Applicant: Intel Corporation
Inventor： Suresh V. Pothukuchi , Andrew Alduino , Ravindranath V. Mahajan , Srikant Nekkanty , Ling Liao , Harinadh Potluri , David M. Bond , Sushrutha Reddy Gujjula , Donald Tiendung Tran , David Hui , Vladimir Tamarkin
IPC: H01L25/16 , H01L23/367 , H01L23/40 , H01L23/473 , H01L23/538 , H04Q11/00
Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.
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公开(公告)号：US20170286353A1
公开(公告)日：2017-10-05
申请号：US15621825
申请日：2017-06-13
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , Wayne Genetti , David Schweitzer
CPC classification number: G06F13/4282 , G06F1/16 , G06F1/185 , G06F1/186 , G06F13/4022 , G06F13/409 , G06F2213/0026 , H01R12/716 , H01R12/721 , H01R12/722 , H01R12/727 , H01R12/73 , H01R12/737 , H05K1/0296 , H05K1/145 , H05K3/308 , H05K5/0286 , H05K7/1422 , H05K2201/10
Abstract: Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.
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5.发明申请REDUCING TRACE LENGTH AND INSERTION LOSS OF HIGH SPEED SIGNALS ON A NETWORK SWITCH BOARD 审中-公开降低网络开关板上的高速信号的跟踪长度和插入损耗公开(公告)号：US20160183402A1
公开(公告)日：2016-06-23
申请号：US14581962
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , William F. Federer , Thomas W. Genetti
IPC: H05K7/14 , H04L12/935
CPC classification number: H04L49/30 , H05K1/117 , H05K2201/0784 , H05K2201/09163 , H05K2201/09227
Abstract: An electrical device can include a printed circuit board (PCB), an electrical component integrated therewith, and connectors that are each integrated with a certain edge of the PCB. Traces can provide electrical channels between the connectors and the electrical component. Some of the connectors can be integrated at a first edge of the PCB and within a first plane, and other connectors can be integrated at a second edge of the PCB and within a second plane that is distinct from the first plane.
Abstract translation: 电气设备可以包括印刷电路板（PCB），与其集成的电气部件，以及每个与PCB的某一边缘集成的连接器。 轨迹可以在连接器和电气部件之间提供电气通道。 一些连接器可以集成在PCB的第一边缘处并在第一平面内，并且其它连接器可以集成在PCB的第二边缘处并且在与第一平面不同的第二平面内。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160181711A1
公开(公告)日：2016-06-23
申请号：US14581119
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Wayne Genetti , Vladimir Tamarkin
CPC classification number: H01R12/71 , G02B6/2804 , G02B6/4452 , G02B6/4463 , G06F1/189 , G06F13/4022 , H01R43/205
Abstract: A cabled midplane interconnect system includes a cabled midplane interconnect having a first connection and a second connection. A first circuit board has a third connection configured to be coupled to the first connection. A second circuit board has a fourth connection configured to be coupled to the second connection. The connection orientations are assigned such that a midplane cable, having a plurality of conductors, couples the first connection to the second connection so that none of the plurality of conductors crosses another of the plurality of conductors.
Abstract translation: 有线中面板互连系统包括具有第一连接和第二连接的有线中平面互连。 第一电路板具有被配置为耦合到第一连接的第三连接。 第二电路板具有被配置为耦合到第二连接的第四连接。 分配连接方向，使得具有多个导体的中平面电缆将第一连接耦合到第二连接，使得多个导体中没有一个导体与多个导体中的另一个导体交叉。
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公开(公告)号：US11830863B2
公开(公告)日：2023-11-28
申请号：US17539088
申请日：2021-11-30
Applicant: Intel Corporation
Inventor： Suresh V. Pothukuchi , Andrew Alduino , Ravindranath V. Mahajan , Srikant Nekkanty , Ling Liao , Harinadh Potluri , David M. Bond , Sushrutha Reddy Gujjula , Donald Tiendung Tran , David Hui , Vladimir Tamarkin
IPC: H01L25/16 , H01L23/367 , H01L23/40 , H01L23/473 , H01L23/538 , H04Q11/00
CPC classification number: H01L25/167 , H01L23/367 , H01L23/40 , H01L23/4006 , H01L23/473 , H01L23/5385 , H01L23/5386 , H04Q11/0005 , H01L2023/4031 , H04Q2011/0039
Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.
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公开(公告)号：US09917392B2
公开(公告)日：2018-03-13
申请号：US15231391
申请日：2016-08-08
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , Wayne Genetti , Keith Mease , Mark Wessel
IPC: H01R13/502 , H01R43/20 , H04L12/931 , H04Q1/02
CPC classification number: H01R13/502 , H01R43/20 , H04L49/40 , H04Q1/15
Abstract: A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.
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公开(公告)号：US09697160B2
公开(公告)日：2017-07-04
申请号：US14581119
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Wayne Genetti , Vladimir Tamarkin
CPC classification number: H01R12/71 , G02B6/2804 , G02B6/4452 , G02B6/4463 , G06F1/189 , G06F13/4022 , H01R43/205
Abstract: A cabled midplane interconnect system includes a cabled midplane interconnect having a first connection and a second connection. A first circuit board has a third connection configured to be coupled to the first connection. A second circuit board has a fourth connection configured to be coupled to the second connection. The connection orientations are assigned such that a midplane cable, having a plurality of conductors, couples the first connection to the second connection so that none of the plurality of conductors crosses another of the plurality of conductors.
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公开(公告)号：US09413097B2
公开(公告)日：2016-08-09
申请号：US14578707
申请日：2014-12-22
Applicant: Intel Corporation
Inventor： Vladimir Tamarkin , Wayne Genetti , Keith Mease , Mark Wessel
IPC: H01R13/502 , H01R43/20
CPC classification number: H01R13/502 , H01R43/20 , H04L49/40 , H04Q1/15
Abstract: A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either side of the cabled midplane. The first connector set and the second connector set include connector slices. A wiring sub-layer includes cable slices to provide a connection between the first connector slice of a connector of the first connector set to the first connector slice of a connector of the second connector set, such that the first wiring sub-layer connects each connector of the first connector set, through one cable slice, to a connector of the second connector set. Additional wiring sub-layers are added, and a second support plate, parallel to the first support plate, is provided to encase and support the wiring sub-layers between the first support plate and the second support plate. Other apparatuses and methods are described.
Abstract translation: 电缆中平面包括沿着连接到有线中平面两侧的线路卡的第一连接器组和第二连接器组之间的平面的第一支撑板。 第一连接器组和第二连接器组包括连接器片。 布线子层包括电缆片，以在第一连接器组件的连接器的第一连接器切片与第二连接器组的连接器的第一连接器片之间提供连接，使得第一布线子层将每个连接器 的第一连接器组，通过一个电缆片，连接到第二连接器组的连接器。 添加附加的布线子层，并且设置平行于第一支撑板的第二支撑板以包围并支撑第一支撑板和第二支撑板之间的布线子层。 描述其他设备和方法。
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