公开(公告)号：US09405340B2

公开(公告)日：2016-08-02

申请号：US13928724

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Baskaran Ganesan ,  Eric Dehaemer ,  Vinod Ambrose ,  Harjinder Hullon ,  Joseph Doucette ,  Seow Fung Ooi ,  Min Huang ,  Zhiguo Wang ,  Yin-Lung Lu ,  William Johnson Bowhill

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括分组为多个群集的多个核心。 基于在多个频率中的每一个处的每个核心的对应的工作电压来形成簇。 每个集群包括唯一的一组核心，并且至少一个集群包括至少两个核心。 所述处理器还包括功率控制单元（PCU），其响应于对第一集群的第一核心的频率变化请求而包括频率/电压控制逻辑，以从第一集群电压 - 频率（ VF）表与第一个集群关联。 第一簇V-F表在第一簇的核的多个操作频率的每一个上唯一地指定对应的工作电压。 描述和要求保护其他实施例。

公开(公告)号：US09959939B2

公开(公告)日：2018-05-01

申请号：US14581686

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Min Huang ,  Zhiguo Wang

IPC: G06F12/06 ,  G11C29/00 ,  G06F11/08 ,  G06F12/0895 ,  G06F11/00 ,  G11C15/04 ,  G06F11/10 ,  G06F11/16

CPC classification number: G11C29/78 ,  G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1064 ,  G06F11/1666 ,  G06F12/0638 ,  G06F12/0895 ,  G11C15/04

Abstract: Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache controller and a cache repair memory communicatively coupled to the cache controller. The cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, in parallel with retrieving the cache data, cache repair data from the cache repair memory, the cache repair data associated with the cache location, the cache repair data comprising at least one of: a bit repair value, a column repair value, and a raw repair value, and output the cache data multiplexed with the cache repair data.

公开(公告)号：US10474526B2

公开(公告)日：2019-11-12

申请号：US15282711

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Min Huang ,  Zhiguo Wang

IPC: G06F11/10 ,  G06F12/0811 ,  G11C29/44 ,  G11C29/00 ,  G06F12/0868 ,  G06F12/0875 ,  G11C29/52 ,  G11C29/04

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

公开(公告)号：US20180095823A1

公开(公告)日：2018-04-05

申请号：US15282711

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Min Huang ,  Zhiguo Wang

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G11C29/52

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

公开(公告)号：US09335803B2

公开(公告)日：2016-05-10

申请号：US13768633

申请日：2013-02-15

Applicant: Intel Corporation

Inventor： Zhiguo Wang ,  David J. Ayers ,  Srikanth Balasubramanian ,  Sukirti Gupta ,  Stefan Rusu ,  Stephen M. Ramey

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/172

Abstract: In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括电压计算逻辑以至少部分地基于多个系数值来计算与多个核的多个活动核心数量相关联的多个最大工作电压值。 以这种方式，处理器可以根据活动核心的数量在不同的最大工作电压下工作。 描述和要求保护其他实施例。