-
公开(公告)号：US20190123751A1
公开(公告)日：2019-04-25
申请号：US16218334
申请日：2018-12-12
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
CPC classification number: H03M1/06 , H03M1/00 , H03M1/0607 , H03M1/1004 , H03M1/1009 , H03M1/12 , H03M1/742 , H03M1/804 , H03M3/30 , H03M3/422 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
-
公开(公告)号：US09559719B1
公开(公告)日：2017-01-31
申请号：US14977341
申请日：2015-12-21
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
IPC: H03M3/00
Abstract: Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier.
Abstract translation: 一些实施例包括使用第一级的装置和方法，该第一级包括积分器，耦合到第一级的第二级，第二级包括放大器，第一电容器和与第一电容器串联耦合的第二电容器，输入节点和 放大器的输出节点，耦合到放大器的输出节点的量化器，以及耦合到量化器的输出节点和第一和第二级的反馈路径，反馈路径包括数模转换器（ DAC），DAC包括耦合到量化器的输出节点的输入节点和耦合到放大器的输入节点的输出节点。
-
公开(公告)号：US09509326B1
公开(公告)日：2016-11-29
申请号：US14736155
申请日：2015-06-10
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
CPC classification number: H03M1/06 , H03M1/00 , H03M1/0607 , H03M1/1004 , H03M1/1009 , H03M1/12 , H03M1/742 , H03M3/30 , H03M3/422 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
Abstract translation: 描述了一种装置，其包括：具有具有p型和n型电流源的DAC单元的数模转换器（DAC）和可调节强度电流源，其可操作以校正DAC单元的非线性 通过p型和n型电流源; 以及耦合到DAC的测量逻辑具有具有p型和n型电流源的参考DAC单元，其中所述测量逻辑用于监视所述p型和n型电流源由所述p型和n型电流源所贡献的积分误差 DAC单元，并且其中测量逻辑是根据参考DAC单元的p型和n型电流源的积分误差和电流来调整可调强度电流源的强度。
-
公开(公告)号：US10581442B2
公开(公告)日：2020-03-03
申请号：US16218334
申请日：2018-12-12
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
-
公开(公告)号：US10243574B2
公开(公告)日：2019-03-26
申请号：US15334218
申请日：2016-10-25
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
-
Patent Agency Ranking
公开(公告)号：US10148278B2
公开(公告)日：2018-12-04
申请号：US15863487
申请日：2018-01-05
Applicant: Intel IP Corporation
Inventor： Marco Bresciani , John G. Kauffman , Udo Schuetz , Patrick Torta , Francesco Conzatti
Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.
-
公开(公告)号：US20180183452A1
公开(公告)日：2018-06-28
申请号：US15863487
申请日：2018-01-05
Applicant: Intel IP Corporation
Inventor： Marco Bresciani , John G. Kauffman , Udo Schuetz , Patrick Torta , Francesco Conzatti
Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.
-
公开(公告)号：US09866227B1
公开(公告)日：2018-01-09
申请号：US15391599
申请日：2016-12-27
Applicant: Intel IP Corporation
Inventor： Marco Bresciani , John G. Kauffman , Udo Schuetz , Patrick Torta , Francesco Conzatti
Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.
-
9.发明申请公开(公告)号：US20170063388A1
公开(公告)日：2017-03-02
申请号：US15334218
申请日：2016-10-25
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
CPC classification number: H03M1/06 , H03M1/00 , H03M1/0607 , H03M1/1004 , H03M1/1009 , H03M1/12 , H03M1/742 , H03M1/804 , H03M3/30 , H03M3/422 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
Abstract translation: 描述了一种装置，其包括：具有具有p型和n型电流源的DAC单元的数模转换器（DAC）和可调节强度电流源，其可操作以校正DAC单元的非线性 通过p型和n型电流源; 以及耦合到DAC的测量逻辑具有具有p型和n型电流源的参考DAC单元，其中所述测量逻辑用于监视所述p型和n型电流源由所述p型和n型电流源所贡献的积分误差 DAC单元，并且其中测量逻辑是根据参考DAC单元的p型和n型电流源的积分误差和电流来调整可调强度电流源的强度。
-
公开(公告)号：US20160365867A1
公开(公告)日：2016-12-15
申请号：US14736155
申请日：2015-06-10
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Udo Schuetz
CPC classification number: H03M1/06 , H03M1/00 , H03M1/0607 , H03M1/1004 , H03M1/1009 , H03M1/12 , H03M1/742 , H03M3/30 , H03M3/422 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.
Abstract translation: 描述了一种装置，其包括：具有具有p型和n型电流源的DAC单元的数模转换器（DAC）和可调节强度电流源，其可操作以校正DAC单元的非线性 通过p型和n型电流源; 以及耦合到DAC的测量逻辑具有具有p型和n型电流源的参考DAC单元，其中所述测量逻辑用于监视所述p型和n型电流源由所述p型和n型电流源所贡献的积分误差 DAC单元，并且其中测量逻辑是根据参考DAC单元的p型和n型电流源的积分误差和电流来调整可调强度电流源的强度。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.024 seconds)
