公开(公告)号：US10283644B2

公开(公告)日：2019-05-07

申请号：US15172576

申请日：2016-06-03

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Norihiro Uemura ,  Takeshi Noda ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: G02F1/1335 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1368 ,  H01L29/24

Abstract: A thin film transistor includes a first oxide semiconductor, a source electrode, a drain electrode, a gate insulating film and a gate electrode. A second oxide semiconductor layer is between the first oxide semiconductor layer and the source electrode. A third oxide semiconductor layer is between the first oxide semiconductor layer and the drain electrode. The content ratio of oxygen/Indium in each of the second semiconductor layer and the third oxide semiconductor layer is equal to or larger than that of the first semiconductor layer. A thickness of each of the second semiconductor layer and the third oxide semiconductor layer is bigger than that of the first semiconductor layer.

公开(公告)号：US09812578B2

公开(公告)日：2017-11-07

申请号：US14920647

申请日：2015-10-22

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Takeshi Noda ,  Hidekazu Miyake ,  Isao Suzumura

IPC: H01L29/786 ,  G02F1/1368 ,  G02F1/1335 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/133602 ,  G02F1/1368 ,  H01L27/1225 ,  H01L29/7869

Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.

公开(公告)号：US09530896B2

公开(公告)日：2016-12-27

申请号：US14658430

申请日：2015-03-16

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Isao Suzumura ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/134372 ,  H01L27/124 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided are a reliable high performance thin film transistor and a reliable high performance display device. The display device has: a gate electrode which is formed on a substrate; a gate insulating film which is formed to cover the substrate and the gate electrode; an oxide semiconductor layer which is formed on the gate electrode through the gate insulating film; a channel protective layer which is in contact with the oxide semiconductor layer and formed on the oxide semiconductor layer; and source/drain electrodes which are electrically connected to the oxide semiconductor layer and formed to cover the oxide semiconductor layer. A metal oxide layer is formed on an upper part of the channel protective layer. The source/drain electrodes are formed to be divided apart on the channel protective layer and the metal oxide layer.

Abstract translation: 提供可靠的高性能薄膜晶体管和可靠的高性能显示器件。 显示装置具有形成在基板上的栅电极; 形成为覆盖基板和栅电极的栅极绝缘膜; 通过栅极绝缘膜形成在栅电极上的氧化物半导体层; 沟道保护层，其与所述氧化物半导体层接触并形成在所述氧化物半导体层上; 以及与氧化物半导体层电连接并形成为覆盖氧化物半导体层的源极/漏极。 金属氧化物层形成在沟道保护层的上部。 源极/漏极形成为在沟道保护层和金属氧化物层上分开。

公开(公告)号：US08853012B2

公开(公告)日：2014-10-07

申请号：US13965418

申请日：2013-08-13

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Takeshi Noda ,  Hidekazu Miyake ,  Isao Suzumura

IPC: H01L21/00 ,  H01L21/84 ,  H01L33/00 ,  H01L21/77

CPC classification number: H01L33/0041 ,  H01L21/77 ,  H01L27/1225 ,  H01L29/7869

Abstract: A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.

Abstract translation: 栅极绝缘膜具有符合栅电极的表面形状的凸部和沿着栅电极的表面从栅电极的周边高度变化的台阶部。 在栅极绝缘膜上设置氧化物半导体层，以具有沟道区域，源极区域和漏极区域的晶体管构成区域，并且与晶体管构成区域分离的覆盖区域和 覆盖栅极绝缘膜的台阶部分。 沟道保护层设置在氧化物半导体层的沟道区上。 源极电极和漏电极分别与氧化物半导体层的源极区域和漏极区域接触。 钝化层设置在源电极和漏电极上。

公开(公告)号：US09947798B2

公开(公告)日：2018-04-17

申请号：US14804395

申请日：2015-07-21

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Norihiro Uemura ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: G02F1/136 ,  H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  G02F1/1368

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a display device includes thin-film transistor. The thin-film transistor includes a first semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a second semiconductor layer, a first electrode and a second electrode. The gap between the bottom surface of the gate electrode and the upper surface of the first channel region of the first semiconductor layer is larger than the gap between the upper surface of the gate electrode and the bottom surface of the second channel region of the second semiconductor layer.

公开(公告)号：US09496292B2

公开(公告)日：2016-11-15

申请号：US13915671

申请日：2013-06-12

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Norihiro Uemura ,  Takeshi Noda ,  Isao Suzumura ,  Toshiki Kaneko

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1244 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/3244

Abstract: The present invention provides a display device having: gate electrodes formed on a transparent substrate; a gate insulating film for covering the gate electrodes; an oxide semiconductor formed on the gate insulating film; drain electrodes and source electrodes formed at a distance from each other with channel regions of the oxide semiconductor in between; an interlayer capacitor film for covering the drain electrodes and source electrodes; common electrodes formed on top of the interlayer capacitor film; and pixel electrodes formed so as to face the common electrodes, and wherein an etching stopper layer for covering the channel regions is formed between the oxide semiconductor and the drain electrodes and source electrodes, the drain electrodes are a multilayer film where a transparent conductive film and a metal film are layered on top of each other, and the drain electrodes and source electrodes make direct contact with the oxide semiconductor.

Abstract translation: 本发明提供一种显示装置，具有：形成在透明基板上的栅电极; 用于覆盖栅电极的栅极绝缘膜; 形成在栅极绝缘膜上的氧化物半导体; 漏电极和源极之间形成有一定距离的氧化物半导体的沟道区; 用于覆盖漏电极和源电极的层间电容膜; 公共电极形成在层间电容器膜的顶部; 以及形成为与公共电极相对的像素电极，并且其中在氧化物半导体与漏电极和源电极之间形成用于覆盖沟道区的蚀刻停止层，漏电极是多层膜，其中透明导电膜和 金属膜层叠在一起，漏电极和源电极与氧化物半导体直接接触。

公开(公告)号：US20160012782A1

公开(公告)日：2016-01-14

申请号：US14793106

申请日：2015-07-07

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Arichika Ishida ,  Norihiro Uemura ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: G09G3/36

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136227 ,  H01L27/1288

Abstract: According to one embodiment, a display device includes a TFT on an insulating substrate. The TFT includes a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and a source electrode and a drain electrode each provided in contact with at least a part of the semiconductor layer. The source and drain electrodes have a laminated structure including a lower layer, an intermediate layer and an upper layer. The source and drain electrodes include sidewalls each including a first tapered portion on the upper layer side, a second tapered portion on the lower layer side and a sidewall protective film attached to the second tapered portion. The taper angle of the first tapered portion is smaller than that of the second tapered portion.

Abstract translation: 根据一个实施例，显示装置包括在绝缘基板上的TFT。 TFT包括栅极电极，栅电极上的绝缘层，绝缘层上的半导体层，以及各自设置成与半导体层的至少一部分接触的源电极和漏电极。 源电极和漏电极具有包括下层，中间层和上层的层压结构。 源电极和漏电极包括侧壁，其各自包括上层侧的第一锥形部分，下层侧上的第二锥形部分和附接到第二锥形部分的侧壁保护膜。 第一锥形部的锥角小于第二锥形部的锥角。

公开(公告)号：US20160027921A1

公开(公告)日：2016-01-28

申请号：US14804395

申请日：2015-07-21

Applicant: Japan Display Inc.

Inventor： Hidekazu MIYAKE ,  Arichika Ishida ,  Norihiro Uemura ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/786 ,  H01L29/24 ,  G02F1/1368 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a display device includes thin-film transistor. The thin-film transistor includes a first semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a second semiconductor layer, a first electrode and a second electrode. The gap between the bottom surface of the gate electrode and the upper surface of the first channel region of the first semiconductor layer is larger than the gap between the upper surface of the gate electrode and the bottom surface of the second channel region of the second semiconductor layer.

Abstract translation: 根据一个实施例，显示装置包括薄膜晶体管。 薄膜晶体管包括第一半导体层，第一绝缘膜，栅电极，第二绝缘膜，第二半导体层，第一电极和第二电极。 栅电极的底表面和第一半导体层的第一沟道区的上表面之间的间隙大于栅电极的上表面和第二半导体的第二沟道区的底表面之间的间隙 层。

公开(公告)号：US09709853B2

公开(公告)日：2017-07-18

申请号：US14480804

申请日：2014-09-09

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Hidekazu Miyake ,  Isao Suzumura ,  Yohei Yamaguchi ,  Toshiki Kaneko

IPC: G02F1/1345 ,  G02F1/1337 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/133788 ,  G02F1/136209 ,  G02F2001/133388

Abstract: To maintain good operation of a peripheral circuit using an oxide thin film transistor in a liquid crystal display panel to which photo alignment is applied, the liquid crystal display panel includes: a transparent substrate provided with an oxide thin film transistor in the periphery of a pixel portion in which pixel electrodes are arranged, to control the pixel electrodes; and an alignment film to align liquid crystal provided in the pixel portion. The alignment film is subjected to photo alignment treatment by ultraviolet irradiation. Further, an ultraviolet absorbing layer is provided so as to cover the oxide thin film transistor. For example, an alignment film is used for the ultraviolet absorbing layer to absorb the ultraviolet light for the photo aliment treatment of the alignment film, in the peripheral circuit portion for controlling the pixel electrodes, thereby preventing the threshold voltage of the oxide thin film transistor from shifting.

公开(公告)号：US09620526B2

公开(公告)日：2017-04-11

申请号：US15015445

申请日：2016-02-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Norihiro Uemura ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/473 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L27/1225 ,  H01L21/02071 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/473 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.