-
公开(公告)号：US08395435B2
公开(公告)日：2013-03-12
申请号：US12615107
申请日：2009-11-09
Applicant: Marco Cassia , Jeremy D. Dunworth
Inventor： Marco Cassia , Jeremy D. Dunworth
IPC: H03K17/687
CPC classification number: H03K17/102 , H03F3/72 , H03K17/693 , H03K2217/0018
Abstract: Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.
Abstract translation: 描述了具有连接体积的开关，用于提高开关性能和用于均匀电压分配的偏置电阻器以提高可靠性 在示例性设计中，开关可以包括耦合在堆叠中的多个晶体管和耦合到堆叠中的至少一个中间节点的至少一个电阻器。 晶体管可以具有（i）施加到堆叠中的第一晶体管的第一电压和（ii）低于施加到晶体管的体节点的第一电压的第二电压。 当晶体管关断时，电阻可以保持晶体管的匹配偏置条件。 在一个示例性设计中，一个电阻器可以耦合在每个晶体管的源极和漏极之间。 在另一示例性设计中，一个电阻器可以耦合在每个中间节点和第一电压之间。 电阻器可以将每个晶体管的源极保持在第一电压。
-
公开(公告)号：US20100255802A1
公开(公告)日：2010-10-07
申请号：US12417512
申请日：2009-04-02
Applicant: Tzu-wang Pan , Yi Zeng , I-Hsiang Lin , Pushp K. Trikha , Jeremy D. Dunworth , Rahul Apte
Inventor： Tzu-wang Pan , Yi Zeng , I-Hsiang Lin , Pushp K. Trikha , Jeremy D. Dunworth , Rahul Apte
IPC: H04B1/16
CPC classification number: H04B1/3805 , H04B15/06
Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.
Abstract translation: 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。
-
公开(公告)号：US07546097B2
公开(公告)日：2009-06-09
申请号：US10092669
申请日：2002-03-06
Applicant: Jeremy D. Dunworth , Brett C. Walker
Inventor： Jeremy D. Dunworth , Brett C. Walker
CPC classification number: H03L7/0898 , H03L7/099 , H03L7/113 , H03L7/199
Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
Abstract translation: 在一个实施例中，本公开描述了一种在无线通信设备中使用的频率合成器或需要精确频率合成但是具有少量噪声的类似设备。 特别地，频率合成器可以包括锁相环（PLL）和集成压控振荡器（VCO）。 频率合成器可以实现一种或多种校准技术来快速且精确地校准VCO。 以这种方式，可以显着地减小VCO的模拟增益，这可以提高无线通信设备的性能。 此外，可以改善PLL的初始状态以减少PLL的锁定时间，这可以增强无线通信设备的性能。
-
公开(公告)号：US08339165B2
公开(公告)日：2012-12-25
申请号：US12632061
申请日：2009-12-07
Applicant: Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri
Inventor： Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri
IPC: H03L7/00
CPC classification number: H03L7/085 , H03L7/089 , H03L7/0891 , H03L7/093
Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.
Abstract translation: 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。
-
公开(公告)号：US08019301B2
公开(公告)日：2011-09-13
申请号：US12140523
申请日：2008-06-17
Applicant: Jeremy D. Dunworth , Brett C. Walker
Inventor： Jeremy D. Dunworth , Brett C. Walker
CPC classification number: H03L7/0898 , H03L7/099 , H03L7/113 , H03L7/199
Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
Abstract translation: 在一个实施例中，本公开描述了一种在无线通信设备中使用的频率合成器或需要精确频率合成但是具有少量噪声的类似设备。 特别地，频率合成器可以包括锁相环（PLL）和集成压控振荡器（VCO）。 频率合成器可以实现一种或多种校准技术来快速且精确地校准VCO。 以这种方式，可以显着地减小VCO的模拟增益，这可以提高无线通信设备的性能。 此外，可以改善PLL的初始状态以减少PLL的锁定时间，这可以增强无线通信设备的性能。
-
Patent Agency Ranking
公开(公告)号：US08254849B2
公开(公告)日：2012-08-28
申请号：US12417512
申请日：2009-04-02
Applicant: Tzu-wang Pan , Yi Zeng , I-Hsiang Lin , Pushp K. Trikha , Jeremy D. Dunworth , Rahul Apte
Inventor： Tzu-wang Pan , Yi Zeng , I-Hsiang Lin , Pushp K. Trikha , Jeremy D. Dunworth , Rahul Apte
IPC: H04B1/06
CPC classification number: H04B1/3805 , H04B15/06
Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.
Abstract translation: 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。
-
公开(公告)号：US07570925B2
公开(公告)日：2009-08-04
申请号：US11436915
申请日：2006-05-18
Applicant: Jeremy D. Dunworth , Brett C. Walker
Inventor： Jeremy D. Dunworth , Brett C. Walker
Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more amplitude calibration techniques prior to enabling the PLL. For example, an amplitude calibration unit may be used to selectively activate switched unit current sources within a tail current source of the VCO. In this manner, the amplitude the signal generated by the oscillator can be adjusted without requiring closed-loop amplitude monitoring or control.
Abstract translation: 在一个实施例中，本公开描述了一种在无线通信设备中使用的频率合成器或需要精确频率合成但是具有少量噪声的类似设备。 特别地，频率合成器可以包括锁相环（PLL）和集成压控振荡器（VCO）。 在使能PLL之前，频率合成器可以实现一个或多个振幅校准技术。 例如，幅度校准单元可用于选择性地激活VCO的尾流源内的开关单元电流源。 以这种方式，可以调节由振荡器产生的信号的幅度，而不需要闭环幅度监视或控制。
-
公开(公告)号：US20080248771A1
公开(公告)日：2008-10-09
申请号：US12140523
申请日：2008-06-17
Applicant: Jeremy D. Dunworth , Brett C. Walker
Inventor： Jeremy D. Dunworth , Brett C. Walker
IPC: H04B1/06
CPC classification number: H03L7/0898 , H03L7/099 , H03L7/113 , H03L7/199
Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
Abstract translation: 在一个实施例中，本公开描述了一种在无线通信设备中使用的频率合成器或需要精确频率合成但是具有少量噪声的类似设备。 特别地，频率合成器可以包括锁相环（PLL）和集成压控振荡器（VCO）。 频率合成器可以实现一种或多种校准技术来快速且精确地校准VCO。 以这种方式，可以显着地减小VCO的模拟增益，这可以提高无线通信设备的性能。 此外，可以改善PLL的初始状态以减少PLL的锁定时间，这可以增强无线通信设备的性能。
-
公开(公告)号：US08446191B2
公开(公告)日：2013-05-21
申请号：US12632053
申请日：2009-12-07
Applicant: Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri , Jifeng Geng , Gurkanwal S. Sahota
Inventor： Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri , Jifeng Geng , Gurkanwal S. Sahota
IPC: H03L7/06
Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
Abstract translation: 锁相环（PLL）装置包括数字微分器，其被配置为区分数字环路信号以至少部分地补偿模拟积分器对模拟电流信号的积分。 数模转换器（DAC）包括基于数字输入信号产生模拟电流信号的电流源输出级。 模拟积分器对模拟电流信号进行积分，以产生用于控制压控振荡器（VCO）的电压控制信号。
-
公开(公告)号：US20110025408A1
公开(公告)日：2011-02-03
申请号：US12615107
申请日：2009-11-09
Applicant: Marco Cassia , Jeremy D. Dunworth
Inventor： Marco Cassia , Jeremy D. Dunworth
IPC: G05F3/02
CPC classification number: H03K17/102 , H03F3/72 , H03K17/693 , H03K2217/0018
Abstract: Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.
Abstract translation: 描述了具有连接体积的开关，用于提高开关性能和用于均匀电压分配的偏置电阻器以提高可靠性。 在示例性设计中，开关可以包括耦合在堆叠中的多个晶体管和耦合到堆叠中的至少一个中间节点的至少一个电阻器。 晶体管可以具有（i）施加到堆叠中的第一晶体管的第一电压和（ii）低于施加到晶体管的体节点的第一电压的第二电压。 当晶体管关断时，电阻可以保持晶体管的匹配偏置条件。 在一个示例性设计中，一个电阻器可以耦合在每个晶体管的源极和漏极之间。 在另一示例性设计中，一个电阻器可以耦合在每个中间节点和第一电压之间。 电阻器可以将每个晶体管的源极保持在第一电压。
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.013 seconds)
