公开(公告)号：US20150303209A1

公开(公告)日：2015-10-22

申请号：US14656115

申请日：2015-03-12

申请人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

发明人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

IPC分类号： H01L27/115 ,  H01L27/112

CPC分类号： H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively.

摘要翻译： 提供了形成半导体器件的半导体器件和方法。 半导体器件可以包括设置在单元阵列电路部分下的外围电路部分。 外围电路部分可以驱动单元阵列电路部分。 半导体器件还可以包括连接到外围电路部分的第一导线和连接到电池阵列电路部分的第二导线。 第一导线和第二导线可以具有基本上相同的形状，并且第一导线可以分别与连接区域中的第二导线重叠。

公开(公告)号：US20140085961A1

公开(公告)日：2014-03-27

申请号：US14037547

申请日：2013-09-26

申请人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

发明人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

公开(公告)号：US20130134377A1

公开(公告)日：2013-05-30

申请号：US13606789

申请日：2012-09-07

申请人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

发明人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

IPC分类号： H01L27/26 ,  H01L27/22

CPC分类号： H01L27/249 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

摘要翻译： 提供半导体存储器件。 该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极 选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

公开(公告)号：US20130285006A1

公开(公告)日：2013-10-31

申请号：US13742598

申请日：2013-01-16

申请人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

发明人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

IPC分类号： H01L45/00

CPC分类号： H01L45/1206 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.

摘要翻译： 可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线， 沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。 可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。

公开(公告)号：US20150170714A1

公开(公告)日：2015-06-18

申请号：US14635588

申请日：2015-03-02

申请人： Jintaek PARK ,  Kohji KANAMORI ,  Youngwoo PARK ,  Jaeduk LEE

发明人： Jintaek PARK ,  Kohji KANAMORI ,  Youngwoo PARK ,  Jaeduk LEE

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

公开(公告)号：US20140198552A1

公开(公告)日：2014-07-17

申请号：US14152440

申请日：2014-01-10

申请人： Jintaek PARK ,  Kohji KANAMORI ,  Youngwoo PARK ,  Jaeduk LEE

发明人： Jintaek PARK ,  Kohji KANAMORI ,  Youngwoo PARK ,  Jaeduk LEE

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

公开(公告)号：US20120098050A1

公开(公告)日：2012-04-26

申请号：US13280759

申请日：2011-10-25

申请人： Jae-Joo SHIM ,  Kyoung-Hoon KIM ,  Woonkyung LEE ,  Wonseok CHO ,  Hoosung CHO ,  Jintaek PARK ,  Jong-Yeon KIM ,  Sung-Min HWANG

发明人： Jae-Joo SHIM ,  Kyoung-Hoon KIM ,  Woonkyung LEE ,  Wonseok CHO ,  Hoosung CHO ,  Jintaek PARK ,  Jong-Yeon KIM ,  Sung-Min HWANG

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.

摘要翻译： 可以提供三维半导体器件。 这些装置可以包括包括栅极图案和绝缘图案的堆叠结构。 堆叠结构还可以包括第一部分和第二部分，并且堆叠结构的第二部分可以具有比第一部分更窄的宽度。 装置还可以包括穿透堆叠结构的活动图案。 所述装置还可以包括与堆栈结构相邻的公共源区。 所述装置还可以包括在公共源区上的捆扎接触塞。

公开(公告)号：US20150340376A1

公开(公告)日：2015-11-26

申请号：US14620770

申请日：2015-02-12

申请人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

发明人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.

摘要翻译： 根据示例性实施例，包括具有单元和连接区域的衬底，堆叠在单元区域上的栅电极，垂直沟道结构，焊盘，虚拟柱以及第一和第二半导体图案的三维半导体器件。 垂直沟道结构穿透最下面的栅电极上的栅极，并且包括第一栅极电介质图案。 焊盘从栅电极延伸并且堆叠在连接区域上。 虚拟柱穿透最低垫上的一些焊盘并且包括第二栅极电介质图案。 第一半导体图案在垂直沟道结构和衬底之间。 第二半导体图案位于虚拟柱和衬底之间。 第一和第二栅极电介质图案可以分别在第一和第二半导体图案上。 第二栅极电介质图案可以覆盖第二半导体图案的整个顶表面。

公开(公告)号：US20120119287A1

公开(公告)日：2012-05-17

申请号：US13297493

申请日：2011-11-16

申请人： Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

发明人： Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

IPC分类号： H01L29/78

CPC分类号： H01L21/823475 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

摘要翻译： 三维（3D）半导体器件包括： 垂直通道，其从靠近基板的下端延伸到上端并连接多个存储单元;以及包括所述多个单元的单元阵列，其中所述单元阵列布置在具有台阶的层的栅堆叠中 结构设置在基板上。 栅极堆叠包括下层，其包括耦合到靠近下端的下部非存储晶体管的下部选择线，上层包括分别耦合到靠近上端的上部非存储晶体管的导线，并且作为单个导电片连接 以形成上部选择线，以及分别包括字线并耦合到单元晶体管的中间层，其中中间层设置在下部选择线和上部选择线之间。

公开(公告)号：US20160163735A1

公开(公告)日：2016-06-09

申请号：US15047392

申请日：2016-02-18

申请人： Sang-Yong PARK ,  Jintaek PARK

发明人： Sang-Yong PARK ,  Jintaek PARK

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/32139 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

摘要翻译： 三维半导体器件包括堆叠结构，其包括堆叠在衬底上的多个导电层，沿着上导电层的侧壁和下导电层之间的第一方向的距离小于沿着侧壁之间的第二方向的距离 所述第一和第二方向彼此交叉并且限定平行于支撑所述基板的表面的平面，以及穿过所述堆叠结构的垂直通道结构。