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    Nonvolatile memory devices
    1.
    发明授权
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US08629489B2

    公开(公告)日：2014-01-14

    申请号：US13357350

    申请日：2012-01-24

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

    摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

    NON-VOLATILE MEMORY DEVICE
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件

    公开(公告)号：US20110079838A1

    公开(公告)日：2011-04-07

    申请号：US12961678

    申请日：2010-12-07

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

    摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

    摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

    Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein
    3.
    发明授权
    Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein 有权
    非易失性存储器件及其操作方法，以抑制其中的寄生电荷积聚

    公开(公告)号：US07864582B2

    公开(公告)日：2011-01-04

    申请号：US12191434

    申请日：2008-08-14

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/16

    摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

    摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

    FLASH MEMORY DEVICES
    5.
    发明申请
    FLASH MEMORY DEVICES 审中-公开
    闪存存储器件

    公开(公告)号：US20090212340A1

    公开(公告)日：2009-08-27

    申请号：US12392656

    申请日：2009-02-25

    申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

    发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/11521

    摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.

    摘要翻译： 一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸 其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20090001451A1

    公开(公告)日：2009-01-01

    申请号：US12146653

    申请日：2008-06-26

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    IPC分类号： H01L21/336 ,  H01L29/792

    CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

    摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

    摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

    Nonvolatile Memory Devices Including a Resistor Region
    7.
    发明申请
    Nonvolatile Memory Devices Including a Resistor Region 审中-公开
    包括电阻器区域的非易失性存储器件

    公开(公告)号：US20080246073A1

    公开(公告)日：2008-10-09

    申请号：US12138712

    申请日：2008-06-13

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
    9.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
    非易失性半导体存储器件

    公开(公告)号：US20080135923A1

    公开(公告)日：2008-06-12

    申请号：US12031096

    申请日：2008-02-14

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译： 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

    Non-volatile semiconductor memory devices
    10.
    发明申请
    Non-volatile semiconductor memory devices 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20080001212A1

    公开(公告)日：2008-01-03

    申请号：US11823397

    申请日：2007-06-27

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译： 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。