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    MEMORY SYSTEM
    1.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230420060A1

    公开(公告)日：2023-12-28

    申请号：US18459501

    申请日：2023-09-01

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya KAMATA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

    IPC: G11C16/32 ,  G11C7/22

    CPC classification number: G11C16/32 ,  G11C7/22

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    3.
    发明公开
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20240295969A1

    公开(公告)日：2024-09-05

    申请号：US18592763

    申请日：2024-03-01

    Applicant: Kioxia Corporation

    Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210081276A1

    公开(公告)日：2021-03-18

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

    IPC: G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

    MEMORY DEVICE AND METHOD
    6.
    发明申请
    MEMORY DEVICE AND METHOD 有权

    公开(公告)号：US20250044990A1

    公开(公告)日：2025-02-06

    申请号：US18922285

    申请日：2024-10-21

    Applicant: Kioxia Corporation

    Inventor： Marie SIA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA ,  Riki SUZUKI

    IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: A memory device includes a data latch, a nonvolatile memory cell array, and a control circuit configured to: manage information about an operation period of a sense operation, the sense operation being an operation in which the control circuit reads data stored in the nonvolatile memory cell array into the data latch, and in response to an inquiry instruction from a memory controller, output, to the memory controller, the information about the operation period of the sense operation.

    MEMORY SYSTEM
    7.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20240385760A1

    公开(公告)日：2024-11-21

    申请号：US18788695

    申请日：2024-07-30

    Applicant: KIOXIA CORPORATION

    Inventor： Shunichi IGAHARA ,  Toshikatsu HIDA ,  Riki SUZUKI ,  Takehiro AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

    MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220261174A1

    公开(公告)日：2022-08-18

    申请号：US17368587

    申请日：2021-07-06

    Applicant: Kioxia Corporation

    Inventor： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

    IPC: G06F3/06

    Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a memory controller. The memory controller receives a write request for data, and determines a unit of a logical-to-physical address conversion which is a conversion between a logical address associated with the data and a physical address of the non-volatile memory into which the data is to be written, according to a size of the data.

    SEMICONDUCTOR MEMORY MEDIUM AND MEMORY SYSTEM
    9.
    发明申请
    SEMICONDUCTOR MEMORY MEDIUM AND MEMORY SYSTEM 有权

    公开(公告)号：US20220130462A1

    公开(公告)日：2022-04-28

    申请号：US17572279

    申请日：2022-01-10

    Applicant: Kioxia Corporation

    Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

    MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210286671A1

    公开(公告)日：2021-09-16

    申请号：US17198451

    申请日：2021-03-11

    Applicant: Kioxia Corporation

    Inventor： Takehiko AMAKI ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

    IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0891

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

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