公开(公告)号：US11694995B2

公开(公告)日：2023-07-04

申请号：US17188308

申请日：2021-03-01

Applicant: Kioxia Corporation

Inventor： Michihito Kono ,  Takashi Izumida ,  Tadayoshi Uechi ,  Takeshi Shimane

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

公开(公告)号：US11527645B2

公开(公告)日：2022-12-13

申请号：US16526025

申请日：2019-07-30

Applicant: KIOXIA CORPORATION

Inventor： Tadayoshi Uechi ,  Takashi Izumida ,  Takeshi Shimane

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

公开(公告)号：USRE49274E1

公开(公告)日：2022-11-01

申请号：US16284203

申请日：2019-02-25

Applicant: KIOXIA CORPORATION

Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC: G11C16/04 ,  G11C16/24

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.