公开(公告)号：US20230101298A1

公开(公告)日：2023-03-30

申请号：US18075601

申请日：2022-12-06

申请人： KIOXIA CORPORATION

发明人： Riki SUZUKI ,  Yoshihisa KOJIMA

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C16/30

摘要： A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US20220083264A1

公开(公告)日：2022-03-17

申请号：US17199586

申请日：2021-03-12

申请人： Kioxia Corporation

发明人： Yoshihisa KOJIMA ,  Riki SUZUKI

IPC分类号： G06F3/06 ,  G06F12/06

摘要： A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.

公开(公告)号：US20210081276A1

公开(公告)日：2021-03-18

申请号：US16806131

申请日：2020-03-02

申请人： KIOXIA CORPORATION

发明人： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC分类号： G06F11/10 ,  G06F3/06

摘要： A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

公开(公告)号：US20230139665A1

公开(公告)日：2023-05-04

申请号：US18092158

申请日：2022-12-30

申请人： Kioxia Corporation

发明人： Marie SIA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA ,  Riki SUZUKI

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

摘要： A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US20230096401A1

公开(公告)日：2023-03-30

申请号：US17694057

申请日：2022-03-14

申请人： Kioxia Corporation

发明人： Masahiro KIYOOKA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC分类号： H03M13/11 ,  H03M13/09 ,  G11C11/4096 ,  G11C11/4074

摘要： A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

公开(公告)号：US20210295921A1

公开(公告)日：2021-09-23

申请号：US17184991

申请日：2021-02-25

申请人： KIOXIA CORPORATION

发明人： Riki SUZUKI ,  Yoshihisa KOJIMA

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

摘要： A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US20220300190A1

公开(公告)日：2022-09-22

申请号：US17468895

申请日：2021-09-08

申请人： Kioxia Corporation

发明人： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Riki SUZUKI

IPC分类号： G06F3/06

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

公开(公告)号：US20220058085A1

公开(公告)日：2022-02-24

申请号：US17519356

申请日：2021-11-04

申请人： KIOXIA CORPORATION

发明人： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC分类号： G06F11/10 ,  G06F3/06

摘要： A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US20210257027A1

公开(公告)日：2021-08-19

申请号：US17018147

申请日：2020-09-11

申请人： Kioxia Corporation

发明人： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

摘要： According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US20210241833A1

公开(公告)日：2021-08-05

申请号：US17038721

申请日：2020-09-30

申请人： KIOXIA CORPORATION

发明人： Kazutaka TAKIZAWA ,  Yoshihisa KOJIMA ,  Masaaki NIIJIMA

IPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C7/04

摘要： A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.