Abstract:
Methods and systems for providing weak pattern (or hotspot) detection and quantification are disclosed. A weak pattern detection and quantification system may include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system may also include at least one processor in communication with the wafer inspection tool. The at least one processor may be configured to: perform pattern grouping on the detected defects based on design of the wafer; identify regions of interest based on the pattern grouping; identify weak patterns contained in the identified regions of interest, the weak patterns being patterns deviating from the design by an amount greater than a threshold; validate the identified weak patterns; and report the validated weak patterns or facilitate revision of the design of the wafer based on the validated weak patterns.
Abstract:
Methods and systems for determining parameter(s) of a process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for determining an area of a defect detected on a specimen. The computer subsystem(s) are also configured for correlating the area of the defect with information for a design for the specimen and determining a spatial relationship between the area of the defect and the information for the design based on results of the correlating. In addition, the computer subsystem(s) are configured for automatically generating a region of interest to be measured during a process performed for the specimen with a measurement subsystem based on the spatial relationship.
Abstract:
A method and system for measuring overlay in a semiconductor manufacturing process comprise capturing an image of a feature in an article at a predetermined manufacturing stage, deriving a quantity of an image parameter from the image and converting the quantity into an overlay measurement. The conversion is by reference to an image parameter quantity derived from a reference image of a feature at the same predetermined manufacturing stage with known overlay (“OVL”). There is also disclosed a method of determining a device inspection recipe for use by an inspection tool comprising identifying device patterns as candidate device care areas that may be sensitive to OVL, deriving an OVL response for each identified pattern, correlating the OVL response with measured OVL, and selecting some or all of the device patterns as device care areas based on the correlation.
Abstract:
Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.
Abstract:
The process for design based assessment includes the following steps. First, the process defines multiple patterns of interest (POIs) utilizing design data of a device and then generates a design based classification database. Further, the process receives one or more inspection results. Then, the process compares the inspection results to each of the plurality of POIs in order to identify occurrences of the POIs in the inspection results. In turn, the process determines yield impact of each POI utilizing process yield data and monitors a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device. Finally, the process determines a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons.
Abstract:
Methods and systems for detecting anomalies in images of a specimen are provided. One system includes one or more computer subsystems configured for acquiring images generated of a specimen by an imaging subsystem. The computer subsystem(s) are also configured for determining one or more characteristics of the acquired images. In addition, the computer subsystem(s) are configured for identifying anomalies in the images based on the one or more determined characteristics without applying a defect detection algorithm to the images or the one or more characteristics of the images.
Abstract:
Methods and systems for finding patterns in a design for a specimen are provided. One system includes one or more computer subsystems configured for searching for a target pattern in a design for a specimen to thereby find multiple instances of the target pattern in the design. The one or more computer subsystems are also configured for separating the multiple instances of the target pattern into different groups based on information for surrounding patterns within a predefined window around the target pattern such that each of the different groups corresponds to a different combination of the target pattern and the surrounding patterns.
Abstract:
A fabricated device having consistent modulation between target and reference components is provided. The fabricated device includes a target component having a first modulation. The fabricated device further includes at least two reference components for the target component including a first reference component and a second reference component, where the first reference component and the second reference component each have the first modulation. Further, a system, method, and computer program product are provided for detecting defects in a fabricated target component using consistent modulation for the target and reference components.
Abstract:
Methods and systems for detecting defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. Different dies are printed on the wafer with different process conditions. The different process conditions correspond to different failure modes for the wafer. The method also includes comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes. In addition, the method includes detecting defects on the wafer based on results of the comparing step.
Abstract:
Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.