公开(公告)号：US20120267790A1

公开(公告)日：2012-10-25

申请号：US13196320

申请日：2011-08-02

Applicant: Kang-Seol LEE ,  Jae-Jin LEE ,  Jae-Hyuk IM

Inventor： Kang-Seol LEE ,  Jae-Jin LEE ,  Jae-Hyuk IM

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract translation: 半导体集成电路包括半导体芯片，垂直穿过半导体芯片形成并被配置为用作第一电源的接口的多个第一通孔通孔和设置在半导体芯片上的第一公共导电层， 多个第一通过芯片通孔在水平方向上彼此相对。

公开(公告)号：US20100073078A1

公开(公告)日：2010-03-25

申请号：US12630657

申请日：2009-12-03

Applicant: Kang-Seol LEE ,  Jae-Hyuk Im

Inventor： Kang-Seol LEE ,  Jae-Hyuk Im

IPC: G05F1/10

CPC classification number: G11C5/14

Abstract: There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract translation: 存在内部电压产生电路，用于通过使响应时间短而提供稳定的高电压。 内部电压产生电路包括电荷泵单元，用于响应于泵送控制信号和电源驱动控制信号而产生高于外部电压的高电压; 泵送控制信号产生单元，用于基于驱动信号将泵送控制信号输出到电荷泵单元; 以及电源驱动控制单元，用于接收驱动信号以向电荷泵单元产生电源驱动控制信号。

公开(公告)号：US20080129373A1

公开(公告)日：2008-06-05

申请号：US12027089

申请日：2008-02-06

Applicant: Kang-Seol LEE ,  Jae-Jin Lee

Inventor： Kang-Seol LEE ,  Jae-Jin Lee

IPC: G05F3/02

CPC classification number: G11C5/145

Abstract: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Abstract translation: 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据访问模式或非数据访问模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US20120153497A1

公开(公告)日：2012-06-21

申请号：US13101660

申请日：2011-05-05

Applicant: Kang-Seol LEE

Inventor： Kang-Seol LEE

IPC: H01L23/48

CPC classification number: H01L24/06 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other. An isolation layer is inserted between the first conductive line and the second conductive line.

Abstract translation: 集成电路包括第一半导体芯片，其包括用于第一电压的多个第一至第二通孔和用于在垂直方向上插入的第二电压的多个第二至第二通孔。 第二半导体芯片堆叠在第一半导体芯片上，并且包括多个第一至第二通孔和多个第二至第二通孔。 多个第一连接焊盘被配置为通过耦合相应的第一通过芯片通孔来将第一半导体芯片耦合到第二半导体芯片。 多个第二连接焊盘被配置为通过耦合相应的第二贯通芯片通孔来将第一半导体芯片耦合到第二半导体芯片。 第一导电线被配置为将多个第一连接焊盘彼此耦合，并且第二导线被配置为将多个第二连接焊盘彼此耦合。 隔离层插入在第一导线和第二导线之间。

公开(公告)号：US20120218019A1

公开(公告)日：2012-08-30

申请号：US13117045

申请日：2011-05-26

Applicant: Kang-Seol LEE ,  Sang-Mook Oh

Inventor： Kang-Seol LEE ,  Sang-Mook Oh

IPC: H03L5/00 ,  H02J1/00

CPC classification number: G11C5/145 ,  G11C11/40 ,  G11C29/12005

Abstract: An internal voltage generating circuit of a semiconductor device includes a normal reference voltage generating unit configured to generate a normal reference voltage having a constant voltage level without regard to PVT variations, a test reference voltage generating unit configured to generate a test reference voltage by dividing a voltage level between an external power supply voltage and the normal reference voltage at a set ratio, an operation reference voltage generating unit configured to generate an operation reference voltage by selecting one of the normal reference voltage and the test reference voltage in response to a test signal, and an internal voltage generating unit configured to generate an internal voltage whose voltage level is determined based on the level of the operation reference voltage.

Abstract translation: 半导体器件的内部电压产生电路包括：正常参考电压生成单元，被配置为在不考虑PVT变化的情况下生成具有恒定电压电平的正常参考电压;测试参考电压产生单元，被配置为通过将 操作基准电压产生单元，被配置为通过响应于测试信号选择正常参考电压和测试参考电压中的一个来产生操作参考电压 以及内部电压产生单元，被配置为基于所述操作参考电压的电平来产生其电压电平被确定的内部电压。

公开(公告)号：US20090323451A1

公开(公告)日：2009-12-31

申请号：US12323221

申请日：2008-11-25

Applicant: Kang-Seol LEE ,  Seok-Cheol Yoon

Inventor： Kang-Seol LEE ,  Seok-Cheol Yoon

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/14 ,  G11C5/063

Abstract: A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh.

Abstract translation: 一种半导体存储器件，其防止在读取操作中在数据输入/输出焊盘处产生的功率噪声影响数据选通信号焊盘。 半导体存储器件包括用于数据输出电路的第一电源电压焊盘，第一电源网和用于数据选通信号输出电路的第二电源电压焊盘。 第一个电源网将第一个电源电压焊盘彼此连接。 第二电源电压焊盘与第一电源网电隔离。

公开(公告)号：US20110234288A1

公开(公告)日：2011-09-29

申请号：US13154680

申请日：2011-06-07

Applicant: Kang-Seol LEE ,  Seok-Cheol Yoon

Inventor： Kang-Seol LEE ,  Seok-Cheol Yoon

IPC: H03L5/00

CPC classification number: G05F1/465 ,  G11C5/147 ,  G11C29/06 ,  G11C29/12005

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract translation: 内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。 内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。 因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。 结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

公开(公告)号：US20100188139A1

公开(公告)日：2010-07-29

申请号：US12727018

申请日：2010-03-18

Applicant: Kang-Seol LEE

Inventor： Kang-Seol LEE

IPC: G05F1/10

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/04

Abstract: A negative voltage supply device includes a negative voltage detector and a negative voltage pumping unit. The negative voltage pumping unit pumps a negative voltage in response to a detection signal. The negative voltage detector detects a level of a negative voltage by using a first element and a second element, which are different in the degree of change in their respective resistance values depending on the temperature, and outputs the detection signal. The detection signal informs the negative voltage pumping unit that pumping of the negative voltage is no longer needed.

Abstract translation: 负电压供给装置包括负电压检测器和负电压抽吸单元。 负电压抽吸单元响应于检测信号泵送负电压。 负电压检测器通过使用根据温度的各自电阻值的变化程度不同的第一元件和第二元件来检测负电压的电平，并输出检测信号。 检测信号通知负电压抽运单元不再需要泵送负电压。

公开(公告)号：US20090267683A1

公开(公告)日：2009-10-29

申请号：US12500305

申请日：2009-07-09

Applicant: Kang-Seol LEE ,  Ji-Eun Jang

Inventor： Kang-Seol LEE ,  Ji-Eun Jang

IPC: G05F1/10

CPC classification number: G05F1/465

Abstract: Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.

Abstract translation: 本发明的实施例旨在提供一种用于产生内部电压的预定稳定电平的半导体存储器件的内部电压发生器。 半导体存储器件包括控制信号发生器，内部电压发生器和内部电压补偿器。 控制信号发生器产生对应于参考信号的电压电平的参考信号和补偿信号。 内部电压发生器响应于参考信号产生内部电压。 内部电压补偿器根据补偿信号补偿内部电压。