公开(公告)号：US5299320A

公开(公告)日：1994-03-29

申请号：US752787

申请日：1991-08-30

申请人： Kunitoshi Aono ,  Masaki Toyokura ,  Toshiyuki Araki ,  Akihiko Ohtani ,  Hisashi Kodama ,  Kiyoshi Okamoto

发明人： Kunitoshi Aono ,  Masaki Toyokura ,  Toshiyuki Araki ,  Akihiko Ohtani ,  Hisashi Kodama ,  Kiyoshi Okamoto

IPC分类号： G06F9/345 ,  G06F9/38 ,  G06F15/78 ,  G06F9/30

CPC分类号： G06F15/8076 ,  G06F9/30036 ,  G06F9/345 ,  G06F9/3885

摘要： In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.

摘要翻译： 在用于执行包括包括用于执行流水线操作的数据处理器的向量流水线指令的多个指令的程序控制类型处理器中，提供了一种程序控制器，其包括程序存储器，程序计数器和解码器，并且还提供有地址生成器 和数据存储器。 当从程序存储器中读出向量流水线指令并由解码器解码时，程序控制器停止程序计数器并输出起始信号，然后根据向量管线的内容来控制数据处理器的操作 指令。 数据处理器通过由程序控制器控制从数据存储器输出的数据执行流水线操作，并且程序控制器在接收到结束之后响应于向量流水线指令检测预定数量的循环执行的流水线操作的完成 信号，然后依次执行向量流水线指令之后的指令。

公开(公告)号：US5293596A

公开(公告)日：1994-03-08

申请号：US658154

申请日：1991-02-20

申请人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

发明人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0207

摘要： A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

公开(公告)号：US5499348A

公开(公告)日：1996-03-12

申请号：US266104

申请日：1994-06-27

申请人： Toshiyuki Araki ,  Kunitoshi Aono ,  Masaki Toyokura

发明人： Toshiyuki Araki ,  Kunitoshi Aono ,  Masaki Toyokura

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.

摘要翻译： 数字处理器包括指令存储器，定序器，解码器和存储器参考控制电路。 在定序器读取外部存储器参考指令的情况下，存储器参考控制电路用于获取从解码器传送的外部存储器参考指令信号和外部存储器参考信号的操作数，保持操作数直到由 外部存储器参考指令终止，并且在循环终止时释放操作数。 当执行外部存储器参考指令时，定序器用于连续地读出后续指令，并且当读出指令参考未被外部存储器参考指令占用的资源时，同时执行读出指令，以便 执行与外部存储器参考指令并行的读出指令，从而提高总处理的吞吐量。

公开(公告)号：US5278781A

公开(公告)日：1994-01-11

申请号：US51273

申请日：1993-04-23

申请人： Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

发明人： Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

IPC分类号： G06F7/544 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F7/5443 ,  G06F17/10 ,  G06F2207/3884

摘要： A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

摘要翻译： 数字信号处理系统包括用于执行流水线处理操作的多个乘法器/累加器。 多个乘法器/累加器中的每一个包括乘法部分和加法部分。 乘法部分包括用于存储乘法器的N个中间输出的N个流水线寄存器。 加法部分包括用于将N + 1个输入的和转换为两个变换输出的华莱士树变换单元和用于将两个变换输出相加的加法器。 N + 1输入包括来自乘法部分的N个中间输出和来自加法器的一个相加输出。

公开(公告)号：US5103419A

公开(公告)日：1992-04-07

申请号：US473760

申请日：1990-02-02

申请人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

发明人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC分类号： G06F7/544

CPC分类号： G06F7/5443 ,  G06F7/49994

摘要： A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.

摘要翻译： 产品总计算电路包括比特扩展电路，其中由乘法器执行的乘法的中间结果的最高有效位从比该位的最高有效位的顺序的一位高的顺序扩展 通过使用由乘法器实现的乘法的两个中间结果中的每一个的最高有效位和乘法输入数据的乘法符号位乘以乘法运算到加法器的相加输入数据的符号位的中间结果。 将具有扩展数据位的数据作为加法执行的加法数据输入加法器。 因此，用于表示乘法器的输出数据的比特数可以与用于通过简单逻辑电路表示加法器的输入数据的比特的比特相加，而不对加法数据添加伪比特。 因此，计算电路的组成元件的数量显着减少。

公开(公告)号：US5517666A

公开(公告)日：1996-05-14

申请号：US185367

申请日：1994-01-24

申请人： Akihiko Ohtani ,  Toshiyuki Araki ,  Kunitoshi Aono ,  Toshihide Akiyama

发明人： Akihiko Ohtani ,  Toshiyuki Araki ,  Kunitoshi Aono ,  Toshihide Akiyama

IPC分类号： G06F15/80 ,  G06F15/347

CPC分类号： G06F15/8092

摘要： A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure, a vector distributor 103 for distributing input data as block vectors to vector memory 304 in each vector processing unit 102, a vector coupler 104 for coupling the block vectors stored in vector memory 404 in each vector processing unit 102 to provide output vectors, an instruction memory 105 for storing the operations of these circuit blocks as an operating program, a sequencer 106 for sequentially reading the instruction memory 105, and a decoder 107 for interpreting the read instructions and outputting a control signal to each circuit block. The scalar processing unit 101 comprises a scalar bus input enabling the scalar processing unit 101 to refer scalar registers in the vector processing units 102. The program controlled processor has improved data processing performance because parallel vector instructions are operated in parallel in the vector processing units of block data distributed by the vector distributor.

摘要翻译： 程序控制处理器包括用于正常数据（=标量）操作和分支处理的标量处理单元101，具有相同结构的多个向量处理单元102，用于将输入数据作为块向量分配给每个矢量存储器304的向量分配器103 矢量处理单元102，用于将存储在矢量存储器404中的块矢量耦合到每个矢量处理单元102中以提供输出矢量的矢量耦合器104，用于存储作为操作程序的这些电路块的操作的指令存储器105，定序器106 用于顺序读取指令存储器105，以及解码器107，用于解读读取指令并向每个电路块输出控制信号。 标量处理单元101包括标量总线输入，使得标量处理单元101能够引用矢量处理单元102中的标量寄存器。程序控制处理器具有改进的数据处理性能，因为并行矢量指令在矢量处理单元中并行操作 由矢量分配器分发的块数据。

公开(公告)号：US06570231B1

公开(公告)日：2003-05-27

申请号：US09652989

申请日：2000-08-31

申请人： Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

发明人： Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L21/823835 ,  H01L21/823871

摘要： An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

摘要翻译： 形成n沟道有源区，p沟道有源区和隔离绝缘膜，通过栅极绝缘膜沉积硅膜。 在n沟道区域中引入n型杂质并将p型杂质引入p沟道区中后，形成硅栅电极，使其宽度仅在n沟道区域之间的边界部分扩大 和p沟道区域。 在形成侧壁绝缘膜，n沟道扩散层和p沟道扩散层之后，在硅栅极，n沟道扩散层和n沟道扩散层的表面上以自对准的方式形成金属硅化物层 p沟道扩散层。

公开(公告)号：US6026486A

公开(公告)日：2000-02-15

申请号：US859308

申请日：1997-05-20

申请人： Hisashi Kodama ,  Kunitoshi Aono

发明人： Hisashi Kodama ,  Kunitoshi Aono

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/30 ,  G06F15/16

CPC分类号： G06F9/3822 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30174 ,  G06F9/30178 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3885

摘要： A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing. Various operations can be performed in parallel, thereby improving processor performance.

摘要翻译： 32位处理器控制单元从存储器接收指令。 然后，控制单元确定接收到的指令是针对32位处理器还是针对16位处理器。 如果接收到的指令被分析为32位处理器指令，则控制单元借助于两个16位指令控制单元控制32位处理器。 如果接收到的指令是16位处理器指令，则32位处理器控制单元向16位指令控制单元中的每一个发送16位处理器模式信号。 两个16位指令控制单元之一控制两个16位处理器中的一个，它们是32位处理器的分区，而另一个16位指令控制单元控制另一个16位处理器。 本发明使得可以根据处理的类型使单个宽的位宽处理器用作多个窄位宽处理器。 可以并行执行各种操作，从而提高处理器的性能。

公开(公告)号：US4635231A

公开(公告)日：1987-01-06

申请号：US662900

申请日：1984-10-19

申请人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

发明人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

IPC分类号： G11C7/10 ,  G11C11/411 ,  G11C11/416 ,  G11C11/40

CPC分类号： G11C11/4116 ,  G11C11/416 ,  G11C7/1024

摘要： To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.

摘要翻译： 为了扩展双极型RAM的功能，将寄存器功能添加到RAM功能。 寄存器功能使得存储在存储单元中的内容被输入到差分开关，并且导出差分开关的输出，以通过简单的电路结构不断地读出存储的所需位的内容。

公开(公告)号：US4635292A

公开(公告)日：1987-01-06

申请号：US682321

申请日：1984-12-17

申请人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

发明人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

IPC分类号： G06T5/20 ,  G06F9/28 ,  G06F15/66 ,  G06K9/36

CPC分类号： G06T5/20

摘要： This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.

摘要翻译： 本发明提供并行部分图像处理，例如使用可以容易地形成为大规模集成电路并可用于各种目的的图像处理器的空间卷积或非线性相邻算术运算。 图像处理器具有加法器 - 减法器，乘法器，互易数存储器，其中地址的倒数和移位量存储在每个地址处，以及移位寄存器。 因此，处理器能够通过将乘数乘以乘法器的倒数并通过移位乘法结果来进行高速分频操作。 此外，通过在程序控制下将输入切换到加法器 - 减法器和乘法器，可以对存储在部分图像存储器中的m行和n列的部分图像数据执行任意加法，减法，乘法和除法 图像处理器。