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    Method of detecting error in a semiconductor memory device
    1.
    发明授权
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US08756475B2

    公开(公告)日：2014-06-17

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/00 ,  H03M13/29 ,  G06F11/08

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Method of detecting error in a semiconductor memory device
    3.
    发明申请
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US20110107191A1

    公开(公告)日：2011-05-05

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device
    4.
    发明授权
    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device 有权
    在半导体存储器件中具有占空比校正电路和内插电路内插时钟信号的半导体存储器件

    公开(公告)号：US06934215B2

    公开(公告)日：2005-08-23

    申请号：US10656303

    申请日：2003-09-04

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/407 ,  H03K5/05 ,  H03K5/156 ,  G11C8/00

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  G11C7/222

    摘要： A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

    摘要翻译： 公开了一种具有占空比校正电路和内插半导体存储器件中的时钟信号的内插电路的半导体存储器件。 半导体存储器件包括占空比校正电路，其接收外部时钟，校正外部时钟的占空比，并输出校正的占空比。 占空比校正电路包括接收外部时钟的第一延迟锁定环，反相外部时钟，使外部时钟与反相外部时钟同步，并输出同步时钟; 接收反相外部时钟的第二个延迟锁定环，将反相外部时钟与外部时钟同步并输出同步时钟; 反相电路，其使所述第一延迟锁定环路的输出信号反相; 内插电路，用第二延迟锁定环的输出信号内插反相电路的输出信号，并输出内插信号; 以及控制电路，其响应于外部时钟的时钟频率信息来控制内插电路。

    Semiconductor memory device and memory system including the same
    5.
    发明授权
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US07882417B2

    公开(公告)日：2011-02-01

    申请号：US11705151

    申请日：2007-02-12

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G11C29/00 ,  H03M13/29

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Spread spectrum clock generator
    6.
    发明授权
    Spread spectrum clock generator 失效
    扩频时钟发生器

    公开(公告)号：US07573932B2

    公开(公告)日：2009-08-11

    申请号：US10837391

    申请日：2004-04-29

    申请人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

    发明人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

    IPC分类号： H04B1/00

    CPC分类号： H04B15/02 ,  G06F1/08 ,  H03K5/133 ,  H03K5/156 ,  H03K2005/00071 ,  H04B2215/067

    摘要： A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.

    摘要翻译： 扩频时钟发生器包括用于存储对应于预定延迟的控制码的非易失性存储器。 延迟电路在一段时间内接收具有确定延迟的预定位数的控制码，以应用于固定时钟信号。 该延迟减轻了周期性时钟信号引起的电磁干扰。

    Semiconductor memory device and memory system including the same
    7.
    发明申请
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US20070204199A1

    公开(公告)日：2007-08-30

    申请号：US11705151

    申请日：2007-02-12

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G11C29/00

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Semiconductor device and method of outputting data therein
    8.
    发明授权
    Semiconductor device and method of outputting data therein 失效

    公开(公告)号：US06590421B2

    公开(公告)日：2003-07-08

    申请号：US10101475

    申请日：2002-03-19

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

    IPC分类号： H03K190175

    CPC分类号： H03K19/00323

    摘要： A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

    Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
    9.
    发明授权
    Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same 有权
    集成电路芯片堆叠具有最初相同的裸片，其具有熔丝和其制造方法

    公开(公告)号：US09076770B2

    公开(公告)日：2015-07-07

    申请号：US13569267

    申请日：2012-08-08

    申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    IPC分类号： H01L23/48 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

    CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

    摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化， 将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

    Jitter suppressing delay locked loop circuits and related methods
    10.
    发明授权
    Jitter suppressing delay locked loop circuits and related methods 失效
    抖动抑制延迟锁定环路电路及相关方法

    公开(公告)号：US07212052B2

    公开(公告)日：2007-05-01

    申请号：US10925522

    申请日：2004-08-25

    申请人： Kyu-Hyoun Kim

    发明人： Kyu-Hyoun Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.

    摘要翻译： 提供延迟锁定环路电路，其包括产生延迟锁定环路输出信号的延迟锁定环路和抖动抑制器。 抖动抑制器可以包括延迟电路，其接收延迟锁定环路输出信号并产生延迟锁定环路输出信号的一个或多个延迟版本;以及相位插值器，其接收延迟锁定环路输出信号和一个或多个延迟锁定环路输出信号 延迟锁定环路输出信号。 在本发明的某些实施例中，延迟电路可以包括多个串联连接的延迟单元。 这些延迟单元中的每一个可以在等于输入到延迟锁定环路的外部时钟信号的一个时钟周期的时间延迟输入的信号。