公开(公告)号：US09564216B2

公开(公告)日：2017-02-07

申请号：US14682903

申请日：2015-04-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0064 ,  G11C29/028 ,  G11C29/06 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0066 ,  G11C2013/0083 ,  G11C2029/0409

Abstract: A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.

Abstract translation: 描述了包括包括多个块的存储器单元的阵列的存储器电路。 该电路包括控制器，该控制器包括用于对多个块中的选定块执行程序序列的逻辑。 程序序列包括程序/验证周期的模式。 该电路包括用于将不同模式的程序/验证周期分配给多个块中的不同块的逻辑。 电路包括用于改变分配给多个块中的特定块的特定模式的逻辑。 该电路包括用于维护多个块中的块的统计信息的逻辑，关于分配给块的编程/验证周期的模式的块中的小区的性能。 控制器包括将应力序列应用于所选择的块之一的逻辑，应力序列包括施加到所选块中的一个存储单元的应力脉冲。

公开(公告)号：US09396793B2

公开(公告)日：2016-07-19

申请号：US14276011

申请日：2014-05-13

Applicant: Macronix International Co., Ltd.

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069

Abstract: A phase change memory (PCM), a writing method thereof and a reading method thereof are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for decreasing a resistance of each memory cell. A detection pulse is applied to all of the memory cells of the PCM for detecting the resistance of each memory cell. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells.

Abstract translation: 提供了相变存储器（PCM）及其写入方法及其读取方法。 PCM具有多个存储单元。 写入方法包括以下步骤。 施加至少一个应力脉冲来老化至少一个存储器单元。 将起始脉冲施加到PCM的所有存储单元，以减小每个存储单元的电阻。 检测脉冲被施加到用于检测每个存储单元的电阻的PCM的所有存储单元。 对老化的记忆单元施加设定的脉冲。 复位脉冲施加到非老化的存储单元。

公开(公告)号：US09373382B1

公开(公告)日：2016-06-21

申请号：US14689101

申请日：2015-04-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-I Wu ,  Win-San Khwa ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C11/00 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0083 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

Abstract: A method for healing phase-change memory device includes steps as follows: At least one memory cell comprising a phase-change material with a shifted current-resistance characteristic function (shifted I-R function) is firstly provided. A healing stress is then applied to the phase-change material to transform the shifted I-R function into an initial current-resistance characteristic function (initial I-R function), wherein the shifted I-R function is a translation function of the initial I-R function.

Abstract translation: 用于治愈相变存储器件的方法包括以下步骤：首先提供至少一个包括具有移动的电流电阻特性函数（移位的I-R功能）的相变材料的存储单元。 然后将愈合应力施加到相变材料上，以将移位的I-R功能转换成初始电流电阻特性函数（初始I-R函数），其中移位的I-R函数是初始I-R函数的平移函数。

公开(公告)号：US09336867B2

公开(公告)日：2016-05-10

申请号：US14148545

申请日：2014-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan Lung ,  Ming-Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

Abstract translation: 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

公开(公告)号：US20140376308A1

公开(公告)日：2014-12-25

申请号：US14276011

申请日：2014-05-13

Applicant: Macronix International Co., Ltd.

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069

Abstract: A phase change memory (PCM), a writing method thereof and a reading method thereof are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for decreasing a resistance of each memory cell. A detection pulse is applied to all of the memory cells of the PCM for detecting the resistance of each memory cell. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells.

Abstract translation: 提供了相变存储器（PCM）及其写入方法及其读取方法。 PCM具有多个存储单元。 写入方法包括以下步骤。 施加至少一个应力脉冲来老化至少一个存储器单元。 将起始脉冲施加到PCM的所有存储单元，以减小每个存储单元的电阻。 检测脉冲被施加到用于检测每个存储单元的电阻的PCM的所有存储单元。 对老化的记忆单元施加设定脉冲。 复位脉冲施加到非老化的存储单元。

公开(公告)号：US20160372195A1

公开(公告)日：2016-12-22

申请号：US14838478

申请日：2015-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-I Wu ,  Tien-Yen Wang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value.

Abstract translation: 提供操作方法，操作系统和电阻随机存取存储器（ReRAM）。 操作方法包括以下步骤。 写入电压和写入电流分别设定在第一预定电压值和第一预定电流值。 写入电压和写入电流被施加到用于写入的ReRAM的存储单元。 如果存储单元的读取电流不在预定电流范围内，则验证写入电流是否达到第二预定电流值。 如果写入电流未达到第二预定电流值，则写入电流增加。 验证写入电压是否达到第二预定电压值，如果写入电流达到第二预定电流值。 如果写入电压未达到第二预定电压值，则写入电压增加。

公开(公告)号：US09336879B2

公开(公告)日：2016-05-10

申请号：US14603647

申请日：2015-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan Lung ,  Chao-I Wu ,  Wei-Chih Chien

IPC: H01L21/8242 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  H01L45/06 ,  H01L45/144

Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

Abstract translation: 一种装置包括具有存储元件的第一和第二多个存储单元，以及在第一和第二多个存储单元上的第一和第二封盖材料。 第一和第二封盖材料可以包括较低和较高密度的氮化硅。 存储器元件可以包括可编程电阻存储器材料，并且封盖材料可以接触存储器元件。 第一和第二多个存储器单元可以具有公共的单元结构。 罐中的第一存储器单元可以包括顶部和底部电极，其间具有记忆材料，并且第一封盖材料与记忆材料接触。 控制电路可以对第一和第二多个存储单元应用不同的写入算法。 通过使用不同的封盖材料但是具有相同的单元结构形成第一和第二封盖层，第一和第二组存储器单元可以具有不同的操作存储器特性。

公开(公告)号：US09336878B2

公开(公告)日：2016-05-10

申请号：US14566453

申请日：2014-12-10

Applicant: Macronix International Co., Ltd.

Inventor： Win San Khwa ,  Chao-I Wu ,  Tzu-Hsiang Su ,  Hsiang-Pang Li

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0097 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0033 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2213/79 ,  G11C2213/82

Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.

Abstract translation: 包括相变材料的第一存储单元。 第一存储器单元可编程以存储多个数据值的一个数据值。 多个数据值由第一存储单元的多个非重叠的电阻范围表示。 至少一个测试脉冲被施加到第一存储器单元，以在电阻的中间范围内建立第一存储器单元的单元电阻，在多个非重叠范​​围内的第一和第二相邻范围内的电阻的中间范围 表示多个数据值的电阻。 在将至少一个测试脉冲施加到第一存储器单元之后，根据（i）电阻中间范围内的电池电阻的相对值，确定是否施加至少一个愈合脉冲来修复第一存储器单元，以及 （ii）中间电阻范围内的参考电阻。

公开(公告)号：US20150371704A1

公开(公告)日：2015-12-24

申请号：US14566453

申请日：2014-12-10

Applicant: Macronix International Co., Ltd.

Inventor： Win San Khwa ,  Chao-I Wu ,  Tzu-Hsiang Su ,  Hsiang-Pang Li

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0033 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2213/79 ,  G11C2213/82

Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.

Abstract translation: 包括相变材料的第一存储单元。 第一存储器单元可编程以存储多个数据值的一个数据值。 多个数据值由第一存储单元的多个非重叠的电阻范围表示。 至少一个测试脉冲被施加到第一存储器单元，以在电阻的中间范围内建立第一存储器单元的单元电阻，在多个非重叠范​​围内的第一和第二相邻范围内的电阻的中间范围 表示多个数据值的电阻。 在将至少一个测试脉冲施加到第一存储器单元之后，根据（i）电阻中间范围内的电池电阻的相对值，确定是否施加至少一个愈合脉冲来修复第一存储器单元，以及 （ii）中间电阻范围内的参考电阻。

公开(公告)号：US08908426B2

公开(公告)日：2014-12-09

申请号：US13693816

申请日：2012-12-04

Applicant: Macronix International Co., Ltd.

Inventor： Tien-Yen Wang ,  Chao-I Wu ,  Chun-Hsiung Hung

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C7/06

CPC classification number: G11C7/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

Abstract: A cell sensing circuit for a phase changing memory and methods thereof are provided. A specific one of the proposed methods includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell; establishing a cell voltage on a cell side and a reference voltage on a reference side respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage.

Abstract translation: 提供了一种用于相变存储器的单元感测电路及其方法。 所提出的方法中的具体方法包括：提供具有读出放大器的感测电路和分别由参考单元和目标单元接收的两个相同的稳定电流; 通过两个相同的稳定电流分别在单元侧建立电池电压和参考侧上的参考电压; 以及使用所述读出放大器基于所述参考电压和所述单元电压之间的电压差来确定所述目标单元的逻辑状态。