-
公开(公告)号：US09564216B2
公开(公告)日：2017-02-07
申请号：US14682903
申请日：2015-04-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pang Li
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0064 , G11C29/028 , G11C29/06 , G11C29/50 , G11C29/50008 , G11C2013/0066 , G11C2013/0083 , G11C2029/0409
Abstract: A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.
Abstract translation: 描述了包括包括多个块的存储器单元的阵列的存储器电路。 该电路包括控制器，该控制器包括用于对多个块中的选定块执行程序序列的逻辑。 程序序列包括程序/验证周期的模式。 该电路包括用于将不同模式的程序/验证周期分配给多个块中的不同块的逻辑。 电路包括用于改变分配给多个块中的特定块的特定模式的逻辑。 该电路包括用于维护多个块中的块的统计信息的逻辑，关于分配给块的编程/验证周期的模式的块中的小区的性能。 控制器包括将应力序列应用于所选择的块之一的逻辑，应力序列包括施加到所选块中的一个存储单元的应力脉冲。
-
公开(公告)号：US09760478B2
公开(公告)日：2017-09-12
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
-
公开(公告)号：US09478288B1
公开(公告)日：2016-10-25
申请号：US14687998
申请日：2015-04-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pang Li , Yu-Ming Chang
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C2013/0088 , G11C2013/0092 , G11C2213/77
Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.
Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。
-
公开(公告)号：US20160307627A1
公开(公告)日：2016-10-20
申请号：US14687998
申请日：2015-04-16
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pang Li , Yu-Ming Chang
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C2013/0088 , G11C2013/0092 , G11C2213/77
Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.
Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。
-
公开(公告)号：US09558823B1
公开(公告)日：2017-01-31
申请号：US14846393
申请日：2015-09-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pan Li , Meng-Fan Chang
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0092
Abstract: A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.
Abstract translation: 提供一种用于操作包括包括可编程电阻存储器元件的存储单元阵列的存储器件的方法。 阵列中的存储单元被编程为通过向存储器单元施加编程脉冲来存储数据，以建立指定范围电阻数量N内的电阻电平，其中每个指定范围对应于特定数据值。 对存储器单元执行漂移恢复处理，包括将具有脉冲形状的恢复脉冲施加到一组编程存储器单元，其中该组中的存储单元具有在指定电阻范围内的两个或更多个内的电阻电平。
-
Patent Agency Ranking
公开(公告)号：US09312029B2
公开(公告)日：2016-04-12
申请号：US14309920
申请日：2014-06-20
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su
CPC classification number: G11C29/12 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/50008 , G11C2013/0092 , G11C2029/0409 , G11C2211/563 , G11C2211/5644 , G11C2211/5646
Abstract: A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell array has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
Abstract translation: 提供了存储器件和相关联的控制方法。 存储器件包括存储单元阵列，感测单元和控制器。 存储单元阵列具有多个存储单元。 感测单元电连接到存储单元阵列和控制器。 感测单元感测多个存储单元的存储单元的特性。 控制器确定存储器单元之一的特性是否偏离，从而控制存储单元阵列。
-
7.发明授权公开(公告)号：US11775822B2
公开(公告)日：2023-10-03
申请号：US16885638
申请日：2020-05-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shih-Hung Chen , Tzu-Hsiang Su
Abstract: A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.
-
公开(公告)号：US09620210B2
公开(公告)日：2017-04-11
申请号：US15094993
申请日：2016-04-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su , Hsiang-Pang Li
CPC classification number: G11C13/0097 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/0069 , G11C29/50008 , G11C2213/79 , G11C2213/82
Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
-
公开(公告)号：US20150255126A1
公开(公告)日：2015-09-10
申请号：US14309920
申请日：2014-06-20
Applicant: Macronix International Co., Ltd.
Inventor： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su
CPC classification number: G11C29/12 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/50008 , G11C2013/0092 , G11C2029/0409 , G11C2211/563 , G11C2211/5644 , G11C2211/5646
Abstract: A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
Abstract translation: 提供了存储器件和相关联的控制方法。 存储器件包括存储单元阵列，感测单元和控制器。 存储单元具有多个存储单元。 感测单元电连接到存储单元阵列和控制器。 感测单元感测多个存储单元的存储单元的特性。 控制器确定存储单元之一的特性是否偏离，从而控制存储单元阵列。
-
公开(公告)号：US20160155516A1
公开(公告)日：2016-06-02
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
Abstract translation: 提供了一种用于存储器件的读取调平方法。 存储器件包括第一存储器块和至少第二存储器块。 读取调平方法包括以下步骤。 确定第一存储块的块读取计数是否大于或等于第一阈值。 当第一存储器块的块读取计数大于或等于第一阈值时，检测第一存储器块的页面的页面读取计数。 确定第一存储块的块读取计数是否大于或等于第二阈值。 当第一存储器块的块读取计数大于或等于第二阈值时，将第一存储器块的页面之一的数据移动到第二存储器块的页面。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.017 seconds)
