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    Operation method of memory device
    2.
    发明授权
    Operation method of memory device 有权

    公开(公告)号：US11289132B1

    公开(公告)日：2022-03-29

    申请号：US17168215

    申请日：2021-02-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Chieh Cheng ,  Yin-Jen Chen

    IPC: G11C7/00 ,  G11C11/00 ,  G11C5/14 ,  G11C8/08

    Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.

    Program method including multiple precharge steps for memory device
    3.
    发明授权
    Program method including multiple precharge steps for memory device 有权

    公开(公告)号：US11322207B1

    公开(公告)日：2022-05-03

    申请号：US17137461

    申请日：2020-12-30

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Chia-Hong Lee ,  Yin-Jen Chen

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24

    Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.

    DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY
    4.
    发明申请
    DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY 有权
    一次性可编程存储器的二极管阵列

    公开(公告)号：US20140050006A1

    公开(公告)日：2014-02-20

    申请号：US14063284

    申请日：2013-10-25

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

    IPC: G11C17/16

    CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

    Abstract translation: 一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体 并且设置成与第一行导体相邻并且与第二行导体相邻。 阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

    Method and system to determine quick pass write operation in increment step pulse programming operation
    5.
    发明授权
    Method and system to determine quick pass write operation in increment step pulse programming operation 有权

    公开(公告)号：US10796753B1

    公开(公告)日：2020-10-06

    申请号：US16667653

    申请日：2019-10-29

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Yin-Jen Chen

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

    Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour. The shrinkage-quantity topographic contour and the program-shot-number topographic contour are overlapped to determine an operation region formed from an application range of the bit line voltage and an application range of the voltage difference value.

    Transistor and circuit using same
    7.
    发明授权
    Transistor and circuit using same 有权
    晶体管和电路使用相同

    公开(公告)号：US09466371B2

    公开(公告)日：2016-10-11

    申请号：US14446037

    申请日：2014-07-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yi-Peng Chang ,  Yin-Jen Chen

    IPC: H01L29/76 ,  G11C16/08 ,  H01L29/40 ,  G11C16/04 ,  H01L27/02

    CPC classification number: G11C16/08 ,  G11C16/0466 ,  H01L27/0251 ,  H01L29/402 ,  H01L29/404

    Abstract: A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor.

    Abstract translation: 描述了包括飞越导体的晶体管。 晶体管具有栅极，沟道和源极/漏极端子。 飞越导体设置在源极/漏极端子上。 电路连接到飞越导体以施加倾向于抵消陷在绝缘材料中的电荷晶体管的影响的偏置电压。 字线驱动器可以包括具有飞越导体的晶体管。

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