公开(公告)号：US10649487B2

公开(公告)日：2020-05-12

申请号：US16143841

申请日：2018-09-27

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Aditya Nukala

IPC: G06F1/04 ,  G06F11/16 ,  G06F1/14 ,  G06F1/10 ,  G06F1/08

Abstract: A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

公开(公告)号：US10114776B2

公开(公告)日：2018-10-30

申请号：US15498846

申请日：2017-04-27

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40 ,  G06F13/34

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US09336122B2

公开(公告)日：2016-05-10

申请号：US13888370

申请日：2013-05-07

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。

公开(公告)号：US20130318408A1

公开(公告)日：2013-11-28

申请号：US13888357

申请日：2013-05-06

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

公开(公告)号：US10536156B1

公开(公告)日：2020-01-14

申请号：US16162135

申请日：2018-10-16

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Kevin Kilzer ,  Prashanth Pulipaka

IPC: H03M1/12

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.

公开(公告)号：US20180121380A1

公开(公告)日：2018-05-03

申请号：US15498846

申请日：2017-04-27

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC: G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/34 ,  G06F13/4068

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US20170168980A1

公开(公告)日：2017-06-15

申请号：US15373219

申请日：2016-12-08

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4282 ,  G06F1/10 ,  G06F13/4291

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

公开(公告)号：US09590649B2

公开(公告)日：2017-03-07

申请号：US14883842

申请日：2015-10-15

Applicant: Microchip Technology Incorporated

Inventor： James E. Bartling ,  Igor Wojewoda ,  Kevin Kilzer

IPC: H03M1/12 ,  H03K17/96 ,  G06F1/32 ,  H03M1/00 ,  H03M1/50

CPC classification number: H03M1/12 ,  G06F1/32 ,  H03K17/9622 ,  H03K2217/960725 ,  H03M1/00 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/50

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract translation: 微编码序列器控制独立于中央处理单元（CPU）的复杂转换序列。 微编码提供了轻松添加新的流程步骤和/或更新现有的流程步骤。 与诸如模数转换器（ADC）或充电时间测量单元（CTMU）之类的模数转换模块和数字处理电路组合的这种可编程序排序器可被配置为独立于CPU 与微编码序列器结合使用。 因此，当CPU和其他高功率模块处于低功耗睡眠模式时，能够以低功耗模式提供自给自足的操作。 这样的外设可以执行数据收集和处理，然后在需要时唤醒CPU，从而节省电力。 此外，该外设不需要CPU处理，因此需要CPU控制的时间关键应用程序可以更有效地运行，同时减少运营负担。

公开(公告)号：US20150019775A1

公开(公告)日：2015-01-15

申请号：US14197721

申请日：2014-03-05

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Kevin Kilzer ,  Sean Steedman

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4282 ,  G06F13/36 ,  G06F13/4295

Abstract: A microcontroller has a housing with external pins and an integrated debugging interface using only a single signal pin. In a method for operating a microcontroller as described above, the method includes the step of debugging or programming the microcontroller using only a single signal pin of the external pins.

Abstract translation: 微控制器具有外部引脚和仅使用单个信号引脚的集成调试接口。 在如上所述的用于操作微控制器的方法中，该方法包括仅使用外部引脚的单个信号引脚来调试或编程微控制器的步骤。

公开(公告)号：US11101812B2

公开(公告)日：2021-08-24

申请号：US16731534

申请日：2019-12-31

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Kevin Kilzer ,  Prashanth Pulipaka

IPC: H03M1/12

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.