公开(公告)号：US10157926B2

公开(公告)日：2018-12-18

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20150001605A1

公开(公告)日：2015-01-01

申请号：US14487201

申请日：2014-09-16

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Jaydip Guha

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L21/28114 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/78

Abstract: A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture.

Abstract translation: 一种形成凹陷进入装置的门结构的方法包括：在栅极电介质的相对的侧壁上横向形成一对侧壁，并在第一导电栅极材料的正上方形成。 栅极电介质，第一导电栅极材料和侧壁间隔物被接收在形成半导体材料的沟槽内。 第二导电栅极材料沉积在与第一导电栅极材料电连接的该对侧壁间隔物之间​​的半导体材料沟槽内。 公开了其他实现方式，包括与制造方法无关的凹入式存取装置门结构。

公开(公告)号：US20140315364A1

公开(公告)日：2014-10-23

申请号：US14319201

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20140073100A1

公开(公告)日：2014-03-13

申请号：US14080417

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20190267379A1

公开(公告)日：2019-08-29

申请号：US16412750

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L29/10 ,  H01L29/78

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US10056386B2

公开(公告)日：2018-08-21

申请号：US15664217

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/10 ,  H01L49/02 ,  H01L27/02 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L27/108 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/10864 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/945

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US20180061835A1

公开(公告)日：2018-03-01

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/423 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/108 ,  G11C11/403 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/90 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/7827

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20130164897A1

公开(公告)日：2013-06-27

申请号：US13751537

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  F. Daniel Gealy

IPC: H01L29/40

CPC classification number: H01L21/28079 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract translation: 提供了包括第一和第二源极/漏极区域的晶体管，沟道区域和栅极堆叠，其在衬底上具有第一栅极电介质，第一栅极电介质的介电常数高于二氧化硅的介电常数，以及金属材料 与第一栅极电介质接触，金属材料被掺杂惰性元素。 还提供了包括晶体管的集成电路和形成晶体管的方法。

公开(公告)号：US11094697B2

公开(公告)日：2021-08-17

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/403 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US10854611B2

公开(公告)日：2020-12-01

申请号：US16412750

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/94 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L23/528 ,  H01L29/08

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.