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    Split block decoder for a nonvolatile memory device
    4.
    发明授权
    Split block decoder for a nonvolatile memory device 有权
    用于非易失性存储器件的分割块解码器

    公开(公告)号：US08958244B2

    公开(公告)日：2015-02-17

    申请号：US13836028

    申请日：2013-03-15

    Applicant: MOSAID Technologies Incorporated

    Inventor： Hyoung Seub Rhie

    IPC: G11C11/34 ,  G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

    Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

    Abstract translation: 具有组织成多个存储器块的存储器阵列的非易失性存储器件，具有平面存储单元或单元堆叠。 存储器件的行解码电路被配置为响应于第一行地址来选择多个存储器块的组，并且响应于第二行地址选择用于接收行信号的组的存储器块。 与每组存储器块相关联的行解码电路可以具有大于单个存储器块的行间距间隔的行间距间隔，并且小于或等于对应于该组存储器块的总行间距间隔。

    Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices
    5.
    发明授权
    Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices 有权

    公开(公告)号：US09704580B2

    公开(公告)日：2017-07-11

    申请号：US13830135

    申请日：2013-03-14

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/06 ,  G11C16/14

    CPC classification number: G11C16/06 ,  G11C16/14

    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

    Nonvolatile memory with split substrate select gates and hierarchical bitline configuration
    6.
    发明授权
    Nonvolatile memory with split substrate select gates and hierarchical bitline configuration 有权
    具有分离衬底选择门和分级位线配置的非易失性存储器

    公开(公告)号：US09007834B2

    公开(公告)日：2015-04-14

    申请号：US13830054

    申请日：2013-03-14

    Applicant: Mosaid Technologies Incorporated

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/14

    CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

    Abstract translation: 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。

    U-Shaped Common-Body Type Cell String
    7.
    发明申请
    U-Shaped Common-Body Type Cell String 有权
    U形普通体型细胞串

    公开(公告)号：US20140307508A1

    公开(公告)日：2014-10-16

    申请号：US14046281

    申请日：2013-10-04

    Applicant: MOSAID Technologies Incorporated

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/04

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

    Abstract translation: 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。

    Vertical Gate Stacked NAND and Row Decoder for Erase Operation
    9.
    发明申请
    Vertical Gate Stacked NAND and Row Decoder for Erase Operation 有权
    垂直门堆叠NAND和行解码器，用于擦除操作

    公开(公告)号：US20150092494A1

    公开(公告)日：2015-04-02

    申请号：US14044449

    申请日：2013-10-02

    Applicant: Mosaid Technologies Incorporated

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/16

    CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14

    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

    Abstract translation: 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。

    METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS
    10.
    发明申请
    METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS 有权
    使用无连接电池编程非易失性存储器的方法和系统

    公开(公告)号：US20140133238A1

    公开(公告)日：2014-05-15

    申请号：US13832785

    申请日：2013-03-15

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483

    Abstract: A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.

    Abstract translation: 提供了具有无连接晶体管的非易失性存储器系统，其使用抑制在无连接晶体管中形成反型层源极和漏极以在至少一个串中引起不连续通道。 该系统可以包括由无连接晶体管组成的NAND闪存单元，并且具有一组字线。 在编程操作期间，字母集合中的选定字线被偏置在编程电压上，并且低于足以抑制源极/漏极形成的字线电压被施加在所选字线的源极侧的至少一条字线上，使得 发生通道隔离，从而导致至少串中的不连续通道。

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