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    Memory device and management method thereof
    1.
    发明授权
    Memory device and management method thereof 有权

    公开(公告)号：US12254215B2

    公开(公告)日：2025-03-18

    申请号：US17955555

    申请日：2022-09-29

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Jia-Xing Lin ,  Nai-Ping Kuo ,  Shih-Chou Juan ,  Chien-Hsin Liu ,  Shunli Cheng

    IPC: G06F3/06

    Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

    MEMORY DEVICE AND MANAGEMENT METHOD THEREOF
    2.
    发明公开
    MEMORY DEVICE AND MANAGEMENT METHOD THEREOF 审中-公开

    公开(公告)号：US20240111453A1

    公开(公告)日：2024-04-04

    申请号：US17955555

    申请日：2022-09-29

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Jia-Xing Lin ,  Nai-Ping Kuo ,  Shih-Chou Juan ,  Chien-Hsin Liu ,  Shunli Cheng

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

    PROGRAMMING METHOD, READING METHOD AND OPERATING SYSTEM FOR MEMORY
    7.
    发明申请
    PROGRAMMING METHOD, READING METHOD AND OPERATING SYSTEM FOR MEMORY 有权
    编程方法，存储器的读取方法和操作系统

    公开(公告)号：US20150220390A1

    公开(公告)日：2015-08-06

    申请号：US14173873

    申请日：2014-02-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Chien-Hsin Liu ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  H03M13/15 ,  H03M13/19

    CPC classification number: G06F11/1072 ,  G06F11/1012 ,  H03M13/1575 ,  H03M13/19

    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.

    Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。

    Memory supporting multiple types of operations
    8.
    发明授权
    Memory supporting multiple types of operations 有权

    公开(公告)号：US11742004B2

    公开(公告)日：2023-08-29

    申请号：US17535021

    申请日：2021-11-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan Hung ,  Nai-Ping Kuo ,  Chien-Hsin Liu

    IPC: G11C7/10

    CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1069 ,  G11C7/1096

    Abstract: A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

    Implementing a read setup in 3D NAND flash memory to reduce voltage threshold deviation over time
    9.
    发明授权
    Implementing a read setup in 3D NAND flash memory to reduce voltage threshold deviation over time 有权

    公开(公告)号：US11385839B1

    公开(公告)日：2022-07-12

    申请号：US17242123

    申请日：2021-04-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Chu Chung ,  Chien-Hsin Liu ,  Yu-Chih Yeh

    IPC: G06F3/06

    Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.

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