公开(公告)号：US06806569B2

公开(公告)日：2004-10-19

申请号：US09964811

申请日：2001-09-28

Applicant: James E. Breisch ,  Mark A. Beiley

Inventor： James E. Breisch ,  Mark A. Beiley

IPC: H01L2334

CPC classification number: H01L23/48 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

Abstract translation: 提供了一种用于将功率传递到片上组件（例如缓冲电路）的机制。 这可以包括具有低频传送路径和高频传送路径的封装单元，以及具有片上部件的管芯和在第一节点和第二节点之间并联耦合的电容器件。 芯片还可以包括低频接收路径和高频接收路径。 低频接收路径可以耦合到封装单元上的低频传送路径和第一节点。 高频接收路径可以耦合到封装单元上的高频传输路径和第一节点。 高频接收路径可以包括阻尼电阻器。

公开(公告)号：US07024565B1

公开(公告)日：2006-04-04

申请号：US09466234

申请日：1999-12-17

Applicant: Mark A. Beiley ,  James E. Breisch

Inventor： Mark A. Beiley ,  James E. Breisch

IPC: H04L9/32 ,  G06F12/14 ,  G06F11/30 ,  G06F11/00 ,  G08B23/00

CPC classification number: H01L23/576 ,  G06F21/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit includes a capacitor formed with a dielectric including the dielectric encasing elements of the circuit. A detector detects changes in the capacitance of the capacitor.

Abstract translation: 电路包括形成有电介质的电容器，该电介质包括电路的电介质封装元件。 检测器检测电容器的电容变化。

公开(公告)号：US06933168B2

公开(公告)日：2005-08-23

申请号：US09802464

申请日：2001-03-09

Applicant: Edward J. Bawolek ,  Lawrence T. Clark ,  Mark A. Beiley

Inventor： Edward J. Bawolek ,  Lawrence T. Clark ,  Mark A. Beiley

IPC: G01J3/51 ,  G02B5/00 ,  G02B5/20 ,  H01L27/14 ,  H01L27/146 ,  H01L31/02 ,  H04N5/235 ,  H01L21/00

CPC classification number: H01L27/14636 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14645 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/1469

Abstract: A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.

Abstract translation: 一种采用遮光罩来调制像素颜色响应度的方法和装置。 改进的像素包括具有光接收面积的光电二极管的基板。 第一颜色的滤色器阵列材料设置在基板上方。 像素具有第一相对响应度。 遮光板设置在基板上方以调制像素颜色响应度。 遮光板形成其面积基本上等于由减小因子调节的光接收面积的孔径。 缩小因子是与第二颜色的第二像素相关联的第一相对响应度和第二相对响应度之间的算术运算的结果。

公开(公告)号：US6118482A

公开(公告)日：2000-09-12

申请号：US986499

申请日：1997-12-08

Applicant: Lawrence T. Clark ,  Mark A. Beiley ,  Eric J. Hoffman

Inventor： Lawrence T. Clark ,  Mark A. Beiley ,  Eric J. Hoffman

IPC: H04N5/367 ,  H04N17/00 ,  H04N5/335

CPC classification number: H04N5/367 ,  H04N17/002

Abstract: CMOS pixel sensors have been of interest as replacements for CCD's in imaging applications. Such devices promise lower power and simpler system level design through fewer power supply voltages and higher functional integration. It is difficult and cost ineffective to utilize images to test active pixel sensors. Here, a method and apparatus for electrical testing of CMOS pixel sensors is described which involves electrically writing a pattern into the CMOS pixel sensors for the detection of adjacent cell shorts or stuck at faults as well as verification of read-channel circuit functionality and performance. The invention provides for an electrical testing of CMOS pixel array that is simple, time efficient and cost effective for use in, for example, production.

Abstract translation: 作为CCD成像应用中的替代品，CMOS像素传感器已经成为关注的焦点。 这样的器件通过更少的电源电压和更高的功能集成来承诺更低的功率和更简单的系统级设计。 利用图像测试有源像素传感器是困难和成本无效的。 这里描述了用于CMOS像素传感器的电测试的方法和装置，其涉及将图案电学写入CMOS像素传感器，用于检测相邻单元短路或卡在故障以及读通道电路功能和性能的验证。 本发明提供了CMOS像素阵列的电气测试，其简单，时间高效并且在例如生产中使用成本有效。

公开(公告)号：US5859450A

公开(公告)日：1999-01-12

申请号：US941800

申请日：1997-09-30

Applicant: Lawrence T. Clark ,  Mark A. Beiley

Inventor： Lawrence T. Clark ,  Mark A. Beiley

IPC: H01L27/14 ,  H01L27/146 ,  H01L31/062 ,  H01L31/10 ,  H01L31/113 ,  H01L27/148

CPC classification number: H01L31/113 ,  H01L27/1463 ,  H01L27/14643

Abstract: A photodiode is provided. The photodiode includes an insulative region (IR) that permits passage of light therethrough. The photodiode also includes a substrate region of a first conductivity type and a well region of a second conductivity type. The well is formed within the substrate, beneath the IR. The well is demarcated from the substrate by a first surface. The photodiode further includes a heavily doped region (HDR) of the second conductivity type. The HDR is formed within the IR at a first position. The first surface meets the HDR at substantially the first position.

Abstract translation: 提供光电二极管。 光电二极管包括允许光通过其中的绝缘区域（IR）。 光电二极管还包括第一导电类型的衬底区域和第二导电类型的阱区域。 在衬底内形成阱，在IR之下。 孔通过第一表面与基底划分。 光电二极管还包括第二导电类型的重掺杂区域（HDR）。 HDR在第一位置的IR内形成。 第一个表面在大体上的第一个位置与HDR相遇。

公开(公告)号：US07330993B2

公开(公告)日：2008-02-12

申请号：US10675875

申请日：2003-09-29

Applicant: Mahesh J. Deshmane ,  Mark A. Beiley ,  Luke A. Johnson

Inventor： Mahesh J. Deshmane ,  Mark A. Beiley ,  Luke A. Johnson

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC classification number: G06F13/4072

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括总线和耦合到总线的芯片组。 芯片组通过芯片组检测总线上传输的信号的转换速率。 此外，芯片组根据信号的状态调整转换速率。

公开(公告)号：US06243134B1

公开(公告)日：2001-06-05

申请号：US09032098

申请日：1998-02-27

Applicant: Mark A. Beiley

Inventor： Mark A. Beiley

IPC: H04N314

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H04N5/35527 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/374 ,  H04N5/3745 ,  H04N5/37452

Abstract: A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.

公开(公告)号：US6133862A

公开(公告)日：2000-10-17

申请号：US127310

申请日：1998-07-31

Applicant: Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

Inventor： Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

IPC: H04N5/363 ,  H04N5/374 ,  H04N5/378 ,  H03M1/06

CPC classification number: H04N5/363 ,  H04N5/374 ,  H04N5/378

Abstract: What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

Abstract translation: 公开的是用于减少基于光电二极管的互补金属氧化物（CMOS）传感器中的行复位噪声的装置。 该装置对传感器阵列中的每行像素使用至少一个参考像素。 此外，提供复位噪声消除单元，用于根据从参考像素接收的复位值确定的调整值来调整从特定行中的像素接收的值。 另外，公开了一种使用该装置的方法。 该方法具有向包括参考像素的像素行提供第一复位信号的步骤。 该方法还从集成后的第一行中读出第一组值。 该方法继续向该行提供第二复位信号，并且从该行读取第二组值。 根据从参考像素读出的值的差来计算调整值。

公开(公告)号：US6040592A

公开(公告)日：2000-03-21

申请号：US873987

申请日：1997-06-12

Applicant: Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

Inventor： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

IPC: H04N1/028 ,  C07D491/048 ,  H01L27/146 ,  H01L31/10 ,  H01L31/113 ,  H01L31/068 ,  H01L31/0352

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L31/1136

Abstract: An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

Abstract translation: 一种具有良好对衬底二极管作为光电检测器的图像传感器。 在优选实施例中，利用现代的水银（CMOS）工艺来制造图像传感器。 二极管结上方的场氧化物区域对于可见光是透明的，因此与在非水银工艺上制造的源/漏扩散至衬底光电二极管的器件相比，光电二极管的竞争量子效率。 光电二极管可以作为具有使用相对未修改的数字CMOS工艺的数字电路的传感器阵列的一部分进行集成。 此外，该结构允许光电二极管的光学性质通过修改阱而不会对其内置于另一相同阱中的FET的特性产生有害影响，即接近于一阶。

公开(公告)号：US06522357B2

公开(公告)日：2003-02-18

申请号：US08939808

申请日：1997-09-30

Applicant: Mark A. Beiley ,  Eric J. Hoffman ,  Lawrence T. Clark

Inventor： Mark A. Beiley ,  Eric J. Hoffman ,  Lawrence T. Clark

IPC: H04N314

CPC classification number: H04N5/3595 ,  H04N5/353

Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Abstract translation: 在具有电子快门的像素中，公开了增加电子快门的保持时间的方法。 采用复位信号，在集成完成后立即将二极管节点驱动到预定电压。 采样信号用于控制通过门。 采样信号包括采样信号为负电压的状态。