公开(公告)号：US20070168538A1

公开(公告)日：2007-07-19

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US07720982B2

公开(公告)日：2010-05-18

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07233998B2

公开(公告)日：2007-06-19

申请号：US09816004

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06809734B2

公开(公告)日：2004-10-26

申请号：US09815558

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

IPC分类号： G06T120

CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07644234B2

公开(公告)日：2010-01-05

申请号：US11141700

申请日：2005-05-31

申请人： Nobuo Sasaki ,  Takeshi Yamazaki ,  Atsushi Kunimatsu ,  Hideki Yasukawa

发明人： Nobuo Sasaki ,  Takeshi Yamazaki ,  Atsushi Kunimatsu ,  Hideki Yasukawa

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0844 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6024

摘要： A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.

摘要翻译： 二次纹理缓存由多个纹理单元通常使用，并将纹理数据的一部分存储在主存储器中。 高速缓存控制CPU根据多个纹理单元的高速缓存未命中来控制从主存储器到次纹理高速缓存的再填充操作，以便抑制二次纹理高速缓存中的抖动的发生。 当多个操作单元以预定的时间差访问相同的存储器地址时，高速缓存控制CPU抑制再填充操作的发生。

公开(公告)号：US20050275658A1

公开(公告)日：2005-12-15

申请号：US11141700

申请日：2005-05-31

申请人： Nobuo Sasaki ,  Takeshi Yamazaki ,  Atsushi Kunimatsu ,  Hideki Yasukawa

发明人： Nobuo Sasaki ,  Takeshi Yamazaki ,  Atsushi Kunimatsu ,  Hideki Yasukawa

IPC分类号： G06F12/08 ,  G06F12/00 ,  G09G5/36

CPC分类号： G06F12/0844 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6024

摘要： A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.

摘要翻译： 二次纹理缓存由多个纹理单元通常使用，并将纹理数据的一部分存储在主存储器中。 高速缓存控制CPU根据多个纹理单元的高速缓存未命中来控制从主存储器到次纹理高速缓存的再填充操作，以便抑制二次纹理高速缓存中的抖动的发生。 当多个操作单元以预定的时间差访问相同的存储器地址时，高速缓存控制CPU抑制再填充操作的发生。

公开(公告)号：US08135900B2

公开(公告)日：2012-03-13

申请号：US12236880

申请日：2008-09-24

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

公开(公告)号：US06359624B1

公开(公告)日：2002-03-19

申请号：US09274305

申请日：1999-03-23

申请人： Atsushi Kunimatsu

发明人： Atsushi Kunimatsu

IPC分类号： G06F1516

CPC分类号： G09G5/399 ,  G06T15/005 ,  G09G5/026 ,  G09G5/363 ,  G09G2340/10 ,  G09G2352/00

摘要： An information processing apparatus secures a wide band width in a graphics bus and draws graphics at high speed and low cost. The apparatus employs graphics processing units connected in parallel. Each of the units is formed on a chip and has a graphics processor and a graphics memory, to provide color information and select information. The outputs of the units are selected through a tournament.

摘要翻译： 信息处理装置确保图形总线中的宽带宽，并且以高速和低成本绘制图形。 该装置采用并行连接的图形处理单元。 每个单元形成在芯片上并具有图形处理器和图形存储器，以提供颜色信息和选择信息。 通过比赛选择单位的输出。

公开(公告)号：US08880836B2

公开(公告)日：2014-11-04

申请号：US12970145

申请日：2010-12-16

申请人： Tsutomu Owa ,  Masaki Miyagawa ,  Atsushi Kunimatsu ,  Mari Takada

发明人： Tsutomu Owa ,  Masaki Miyagawa ,  Atsushi Kunimatsu ,  Mari Takada

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F3/0616 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7211 ,  H03M7/6088

摘要： According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.

摘要翻译： 根据一个实施例，一种设备包括确定单元，压缩单元，选择单元，写入更新单元，写入单元。 确定单元基于特定信息确定是否压缩写入数据。 具体信息包括写入数据的类型，数量，访问频率和重要性水平中的至少一个。 当确定压缩写入数据时，压缩单元压缩写入数据。 选择单元基于特定信息来选择非易失性存储器中的写入数据的写入区域。 写入更新单元更新特定信息。 当确定压缩写入数据时，写入单元将压缩写入数据写入写入区域。 当不确定压缩写入数据时，写入单元将未压缩的写入数据写入写入区域。

公开(公告)号：US20080244165A1

公开(公告)日：2008-10-02

申请号：US12056501

申请日：2008-03-27

申请人： Atsushi Kunimatsu

发明人： Atsushi Kunimatsu

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/1045 ,  G06F12/0246 ,  G06F12/10

摘要： An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.

摘要翻译： 设备的示例包括将逻辑地址转换为高速缓存的物理地址的第一MMU，基于高速缓存的物理地址访问高速缓存的控制器，存储向主存储器外部存取访问状态的历史数据的第一存储器 处理器，存储表示主存储器中的逻辑地址和物理地址之间的关系的关系数据的第二存储器，以及基于历史和关系数据将逻辑地址转换为主存储器的物理地址的第二MMU，以及访问 主存储器基于主存储器的物理地址。 第一和第二MMU，控制器，第一存储，第二存储器被包括在处理器中。