公开(公告)号：US20070168538A1

公开(公告)日：2007-07-19

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US07233998B2

公开(公告)日：2007-06-19

申请号：US09816004

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07720982B2

公开(公告)日：2010-05-18

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06809734B2

公开(公告)日：2004-10-26

申请号：US09815558

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

IPC分类号： G06T120

CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US20050120254A1

公开(公告)日：2005-06-02

申请号：US10959700

申请日：2004-10-05

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1/26 ,  G06F12/00

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/3243 ,  G06F9/30145 ,  G06F9/30167 ,  Y02D10/152 ,  Y02D10/16

摘要： A processing element (PE) includes a processing unit (PU) and a number of attached processing units (APUs). The instruction set of each APU is divided a priori into a number of types, each type associated with a different amount of heat generation. Each APU keeps track of the amount of each type of instruction executed over a time period,—the power information,—and provides this power information to the PU. The PU then performs power management as a function of the provided power information from each APU,—such as directing a particular APU to enter an idle state to reduce power consumption.

摘要翻译： 处理单元（PE）包括处理单元（PU）和多个附加处理单元（APU）。 每个APU的指令集被预先划分成多种类型，每种类型与不同的发热量相关联。 每个APU跟踪在一段时间内执行的每种类型的指令的数量 - 功率信息，并将该功率信息提供给PU。 然后，PU根据来自每个APU的所提供的功率信息执行功率管理，例如指示特定APU进入空闲状态以降低功耗。

公开(公告)号：US20050081209A1

公开(公告)日：2005-04-14

申请号：US10967433

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06 ,  G06F9/46

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。

公开(公告)号：US07231500B2

公开(公告)日：2007-06-12

申请号：US10959635

申请日：2004-10-05

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F12/1425 ,  G06F12/0815 ,  G06F12/1483 ,  G06F13/42

摘要： A system configuration includes a processing element (PE), an input/output (I/O) interface device and a shared memory. The PE further includes at least one processing unit (PU) and one, or more, attached processing units (APUs). At least one of the APUs performs an I/O function by reading data from, and writing data to, an external device coupled to the I/O interface device. Data is exchanged between the APU and the I/O interface device via the shared memory using a data level synchronization mechanism.

摘要翻译： 系统配置包括处理元件（PE），输入/输出（I / O）接口设备和共享存储器。 PE还包括至少一个处理单元（PU）和一个或多个附接的处理单元（APU）。 至少一个APU通过从耦合到I / O接口设备的外部设备读取数据和向其写入数据来执行I / O功能。 使用数据级同步机制，通过共享存储器在APU和I / O接口设备之间交换数据。

公开(公告)号：US08321866B2

公开(公告)日：2012-11-27

申请号：US13206968

申请日：2011-08-10

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F9/46

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。

公开(公告)号：US07457939B2

公开(公告)日：2008-11-25

申请号：US10967579

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F9/30

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 提供处理程序和数据的处理系统。 处理系统具有处理单元和多个子处理单元。 每个子处理单元包括用于存储程序和数据的专用本地存储器。 各个子处理单元的专用本地存储器不是高速缓冲存储器。 替代地，多个计算设备可以经由通信网络彼此连接，并且每个计算设备可以包括具有处理单元和子处理单元的至少一个处理单元。

公开(公告)号：US20050078117A1

公开(公告)日：2005-04-14

申请号：US10967363

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于执行图形处理的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器中的一个可以对第一组图形数据执行图形处理，以产生第二组图形数据，另一个第二处理器可以在第二组上执行图形处理，以生成第三组图形数据。