公开(公告)号：US08405184B2

公开(公告)日：2013-03-26

申请号：US12824539

申请日：2010-06-28

申请人： Kou-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su ,  Mei-Ling Chen

发明人： Kou-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su ,  Mei-Ling Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/66143 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/872 ,  H01L29/8725

摘要： A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.

摘要翻译： 提供沟槽肖特基二极管及其制造方法。 沟槽肖特基二极管包括其中具有多个沟槽，栅极氧化物层，多晶硅结构，保护环和电极的半导体衬底。 首先，通过蚀刻步骤在半导体衬底中形成沟槽。 然后，在沟槽中形成栅氧化层和多晶硅结构，并突出在半导体衬底的表面之上。 保护环形成为覆盖所得结构的一部分。 最后，电极形成在防护环的上方，另一部分不被保护环覆盖。 突出的栅极氧化物层和突出的多晶硅结构可以避免在沟槽结构中发生裂纹。

公开(公告)号：US20100327288A1

公开(公告)日：2010-12-30

申请号：US12824539

申请日：2010-06-28

申请人： Kou-Liang CHAO ,  Hung-Hsin Kuo ,  Tse-Chuan Su ,  Mei-Ling Chen

发明人： Kou-Liang CHAO ,  Hung-Hsin Kuo ,  Tse-Chuan Su ,  Mei-Ling Chen

IPC分类号： H01L29/872 ,  H01L21/329 ,  H01L21/04

CPC分类号： H01L29/66143 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/872 ,  H01L29/8725

摘要： A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.

摘要翻译： 提供沟槽肖特基二极管及其制造方法。 沟槽肖特基二极管包括其中具有多个沟槽，栅极氧化物层，多晶硅结构，保护环和电极的半导体衬底。 首先，通过蚀刻步骤在半导体衬底中形成沟槽。 然后，在沟槽中形成栅氧化层和多晶硅结构，并突出在半导体衬底的表面之上。 保护环形成为覆盖所得结构的一部分。 最后，电极形成在防护环的上方，另一部分不被保护环覆盖。 突出的栅极氧化物层和突出的多晶硅结构可以避免在沟槽结构中发生裂纹。

公开(公告)号：US08558315B2

公开(公告)日：2013-10-15

申请号：US13190918

申请日：2011-07-26

申请人： Mei-Ling Chen ,  Hung-Hsin Kuo ,  Kou-Liang Chao

发明人： Mei-Ling Chen ,  Hung-Hsin Kuo ,  Kou-Liang Chao

IPC分类号： H01L29/66

CPC分类号： H01L21/76224 ,  H01L21/761 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66174 ,  H01L29/66477 ,  H01L29/80 ,  H01L29/861 ,  H01L29/94 ,  H01L2924/13091

摘要： A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

公开(公告)号：US20120261751A1

公开(公告)日：2012-10-18

申请号：US13446327

申请日：2012-04-13

申请人： Kou-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

发明人： Kou-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

IPC分类号： H01L29/78

CPC分类号： H01L29/66143 ,  H01L21/28017 ,  H01L21/3086 ,  H01L29/407 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/7813 ,  H01L29/861

摘要： A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.

摘要翻译： 提供一种制造具有垂直MOS结构的整流器的方法。 第一沟槽结构和第一掩模层形成在半导体衬底的第一侧。 第二沟槽结构形成在半导体衬底的第二侧。 栅极氧化层，多晶硅结构和金属溅射层依次形成在第二沟槽结构上。 整流器还包括湿式氧化物层和多个掺杂区域。 在第一多沟槽结构的表面和半导体衬底中形成湿氧化物层。 掺杂区形成在半导体衬底和第二沟槽结构之间的区域上，并且位于掩模层旁边。 金属溅射层形成在对应于第一沟槽结构的第一掩模层上。

公开(公告)号：US08618626B2

公开(公告)日：2013-12-31

申请号：US12902402

申请日：2010-10-12

申请人： Kou-Liang Chao ,  Mei-Ling Chen ,  Tse-Chuan Su ,  Hung-Hsin Kuo

发明人： Kou-Liang Chao ,  Mei-Ling Chen ,  Tse-Chuan Su ,  Hung-Hsin Kuo

IPC分类号： H01L29/66

CPC分类号： H01L29/66143 ,  H01L21/2256 ,  H01L21/28537 ,  H01L29/0623 ,  H01L29/402 ,  H01L29/872

摘要： A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

摘要翻译： 沟槽肖特基整流器件包括具有第一导电类型的衬底，在衬底中形成的多个沟槽，以及形成在沟槽的侧壁上的绝缘层。 沟槽填充有导电结构。 存在覆盖导电结构和衬底的电极，因此在电极和衬底之间形成肖特基接触。 在衬底中形成具有第二导电类型的多个嵌入式掺杂区域，并位于沟槽下方。 每个掺杂区域和衬底形成PN结以夹紧流向肖特基接触的电流，以便抑制电流泄漏。

公开(公告)号：US20120049287A1

公开(公告)日：2012-03-01

申请号：US13190918

申请日：2011-07-26

申请人： Mei-Ling Chen ,  Hung-Hsin Kuo ,  Kou-Liang Chao

发明人： Mei-Ling Chen ,  Hung-Hsin Kuo ,  Kou-Liang Chao

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/76224 ,  H01L21/761 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66174 ,  H01L29/66477 ,  H01L29/80 ,  H01L29/861 ,  H01L29/94 ,  H01L2924/13091

摘要： A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

摘要翻译： 提供了沟槽隔离金属氧化物半导体（MOS）P-N结二极管器件及其制造方法。 沟槽隔离MOS PN结二极管器件是N沟道MOS结构和横向PN结二极管的组合，其中多晶硅填充的沟槽氧化物层被埋在P型结构中以代替大部分P型 结构体。 因此，本发明的沟槽隔离MOS P-N结二极管器件具有肖特基二极管和P-N结二极管的优点。 也就是说，沟槽隔离MOS P-N结二极管器件具有快速的开关速度，低正向压降，低反向漏电流和短的反向恢复时间。

公开(公告)号：US20110084353A1

公开(公告)日：2011-04-14

申请号：US12902402

申请日：2010-10-12

申请人： Kou-Liang CHAO ,  Mei-Ling Chen ,  Tse-Chuan Su ,  Hung-Hsin Kuo

发明人： Kou-Liang CHAO ,  Mei-Ling Chen ,  Tse-Chuan Su ,  Hung-Hsin Kuo

IPC分类号： H01L29/47 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L21/2256 ,  H01L21/28537 ,  H01L29/0623 ,  H01L29/402 ,  H01L29/872

摘要： A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

摘要翻译： 沟槽肖特基整流器件包括具有第一导电类型的衬底，在衬底中形成的多个沟槽，以及形成在沟槽的侧壁上的绝缘层。 沟槽填充有导电结构。 存在覆盖导电结构和衬底的电极，因此在电极和衬底之间形成肖特基接触。 在衬底中形成具有第二导电类型的多个嵌入式掺杂区域，并位于沟槽下方。 每个掺杂区域和衬底形成PN结以夹紧流向肖特基接触的电流，以便抑制电流泄漏。

公开(公告)号：US08664701B2

公开(公告)日：2014-03-04

申请号：US13446327

申请日：2012-04-13

申请人： Kuo-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

发明人： Kuo-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

IPC分类号： H01L21/02 ,  H01L21/322

CPC分类号： H01L29/66143 ,  H01L21/28017 ,  H01L21/3086 ,  H01L29/407 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/7813 ,  H01L29/861

摘要： A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.

摘要翻译： 提供一种制造具有垂直MOS结构的整流器的方法。 第一沟槽结构和第一掩模层形成在半导体衬底的第一侧。 第二沟槽结构形成在半导体衬底的第二侧。 栅极氧化层，多晶硅结构和金属溅射层依次形成在第二沟槽结构上。 整流器还包括湿式氧化物层和多个掺杂区域。 在第一多沟槽结构的表面和半导体衬底中形成湿氧化物层。 掺杂区形成在半导体衬底和第二沟槽结构之间的区域上，并且位于掩模层旁边。 金属溅射层形成在对应于第一沟槽结构的第一掩模层上。

公开(公告)号：US08680590B2

公开(公告)日：2014-03-25

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L21/02 ,  H01L21/44

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。

公开(公告)号：US20130228891A1

公开(公告)日：2013-09-05

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。